Fabrication method of semiconductor integrated circuit device and probe card

• US 7,688,086 B2
• Filed: 11/02/2006
• Issued: 03/30/2010
• Est. Priority Date: 11/11/2005
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Horigome, Yoshimi, Natori, Iwao, Motoyama, Yasuhiro, Nakamura, Seigo
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): ISLA RODAS, RICHARD
• Application Number:
  US11/555,993
• Publication Number:
  US 20070108997A1
• Time in Patent Office: 1,244 Days
• Field of Search: 324754-765, 73855-856
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735

Abstract

To provide a technique of firmly bringing a stylus and a test pad into contact with each other in carrying out a probe testing summarizingly for plural chips by using a prober having the stylus formed by a technique of manufacturing a semiconductor integrated circuit device, plane patterns of respective wirings are formed such that a wiring and a wiring electrically connected to the wiring or a wiring which is not electrically connected to the wiring overlap each other, and a plane pattern arranged with both of the wiring and the wiring is constituted at upper portions of probes. Further, patterns of the wirings are formed such that an interval of arranging the wirings and a density of arranging the wirings become uniform at respective wiring layers in a thin film sheet.

Claims

1. A method of testing a semiconductor integrated circuit, comprising:

positioning a main face of the semiconductor integrated circuit adjacent to a first side of a probe apparatus, the main face of the semiconductor integrated circuit including a plurality of electrodes, and the first side of the probe apparatus including a sheet with a plurality of metal film portions each having a contact probe;

contacting the plurality of electrodes with corresponding ones of the contact probes; and

conducting electrical testing of the semiconductor integrated circuit with the plurality of electrodes in contact with the corresponding contact probes,

wherein said contacting includes controlling a pressing apparatus to move the sheet so as to bring the plurality of electrodes into contact with corresponding ones of the contact probes,

wherein the sheet further includes a first insulating film, a second insulating film, and a plurality of multi-layered wiring portions each having a first wiring portion and a second wiring portion, the first wiring portion being electrically connected to an associated one of the metal film portions,

wherein the first insulating film is formed over the metal film portions,

wherein each first wiring portion is formed over the first insulating film and is electrically connected to the associated metal film portion through a first opening formed in the first insulating film,

wherein the second insulating film is formed over the first wiring portions,

wherein each second wiring portion is formed over the second insulating film and is electrically connected to the corresponding first wiring portion through a second opening formed in the second insulating film,

wherein each first wiring portion overlaps the corresponding second wiring portion in plan view,

wherein each first wiring portion and corresponding second wiring portion overlap the contact probe of the associated metal film portion in plan view, and

wherein each first opening and each second opening do not overlap the contact probe of the associated metal film portion in plan view.

2. The method of claim 1,

wherein a side of the sheet opposite a side having the contact probes includes a portion having no protrusions, and

wherein the pressing apparatus presses the portion of the sheet having no protrusions so as to bring the plurality of electrodes into contact with corresponding ones of the contact probes.

3. The method of claim 1, wherein the first wiring portion and the second wiring portion are formed of plural wiring layers in the sheet.

4. The method of claim 1, wherein the pressing apparatus provides a predetermined force to the sheet at a side opposite to the first side of the probe apparatus so as to bring the plurality of electrodes into contact with corresponding ones of the contact probes.

5. The method of claim 1, wherein the probe apparatus includes a plurality of terminals at a side opposite to the first side of the probe apparatus.

6. The method of claim 5, wherein the plurality of terminals at the side opposite to the first side of the probe apparatus substantially surround the plurality of contact probes in plan view.

7. The method of claim 1, wherein densities of the first and second wiring portions are uniform.

8. The method of claim 1,

wherein widths of the plurality of multi-layered wiring portions are uniform, and

wherein intervals between adjacent ones of the multi-layered wiring portions in plan view are uniform.

9. The method of claim 1,

wherein said integrated semiconductor circuit includes a first integrated semiconductor circuit portion and a second integrated semiconductor circuit portion arranged adjacent to each other, and

wherein said electrical testing is conducted for the first integrated semiconductor circuit portion and for the second integrated semiconductor circuit portion, substantially simultaneously.

10. The method of claim 1, wherein each said metal film portion does not overlap any of the other metal film portions in plan view.

11. The method of claim 1, wherein each first opening does not overlap the associated second opening in plan view.

12. The method of claim 1,

wherein widths of the first wiring portions are uniform,

wherein intervals, in the first direction, between the first wiring portions are uniform, and

wherein intervals, in the first direction, between the second wiring portions are uniform.

13. The method of claim 1,

wherein the metal film portions are spaced from one another in a first direction,

wherein the first wiring portions are spaced from one another in the first direction,

wherein the second wiring portions are spaced from one another in the first direction, and

wherein the first wiring portions and the second wiring portions extend in a second direction perpendicular to the first direction.

14. A method of testing a semiconductor integrated circuit, comprising:

positioning a main face of the semiconductor integrated circuit adjacent to a first side of a probe apparatus, the main face of the semiconductor integrated circuit including a plurality of electrodes, and the first side of the probe apparatus including a sheet with a plurality of elongate metal film portions each having a contact probe;

contacting the plurality of electrodes with corresponding ones of the contact probes; and

conducting electrical testing of the semiconductor integrated circuit with the plurality of electrodes in contact with the corresponding contact probes,

wherein the sheet further includes a first insulating film, a second insulating film, and a plurality of multi-layered wiring portions each having a first wiring portion and a second wiring portion, the first wiring portion being electrically connected to an associated one of the metal film portions,

wherein the first insulating film is formed over the metal film portions,

wherein each first wiring portion is formed over the first insulating film and is electrically connected to the associated metal film portion,

wherein the second insulating film is formed over the first wiring portions,

wherein each second wiring portion is formed over the second insulating film and is electrically connected to the corresponding first wiring portion,

wherein each first wiring portion overlaps the contact probe of the associated metal film portion in plan view such that the first wiring portion extends over the contact probe of the associated metal film portion, with a portion of the first insulating film being arranged therebetween,

wherein each second wiring portion overlaps the contact probe of the associated metal film portion in plan view such that the second wiring portion extends over the contact probe of the associated metal film portion, with the second insulating film being arranged therebetween,

wherein each said contact probe is arranged at a first length wise portion of the associated metal film portion, and each said first wiring portion is electrically connected to a second length wise portion which does not overlap the first length wise portion of the associated metal film portion,

wherein each first wiring portion is coupled to its associated metal film portion at a first coupling portion,

wherein each second wiring portion is coupled to its associated first wiring portion at a second coupling portion, and

wherein each first coupling portion and associated second coupling portion do not overlap each other in plan view.

15. The method of claim 14,

wherein a side of the sheet opposite a side having the contact probes includes a portion having no protrusions, and

wherein a pressing apparatus presses the portion of the sheet having no protrusions so as to bring the plurality of electrodes into contact with corresponding ones of the contact probes.

16. The method of claim 14, wherein the first wiring portion and the second wiring portion are formed of plural wiring layers in the sheet.

17. The method of claim 14, wherein a pressing apparatus provides a predetermined force to the sheet at a side opposite to the first side of the probe apparatus so as to bring the plurality of electrodes into contact with corresponding ones of the contact probes.

18. The method of claim 14, wherein the probe apparatus includes a plurality of terminals at a side opposite the first side of the probe apparatus.

19. The method of claim 18, wherein the plurality of terminals at the side opposite the first side of the probe apparatus substantially surround the plurality of contact probes in plan view.

20. The method of claim 14, wherein densities of the first and second wiring portions are uniform.

21. The method of claim 14,

wherein widths of the plurality of multi-layered wiring portions are uniform, and

wherein intervals between adjacent ones of the multi-layered wiring portions in plan view are uniform.

22. The method of claim 14,

wherein said integrated semiconductor circuit includes a first integrated semiconductor circuit portion and a second integrated semiconductor circuit portion arranged adjacent to each other, and

wherein said electrical testing is conducted for the first integrated semiconductor circuit portion and for the second integrated semiconductor circuit portion, substantially simultaneously.

23. The method of claim 14, wherein each said metal film portion does not overlap any of the other metal film portions in plan view.

24. The method of claim 14,

wherein widths of the first wiring portions are uniform,

wherein intervals, in the first direction, between the first wiring portions are uniform, and

wherein intervals, in the first direction, between the second wiring portions are uniform.

25. The method of claim 14,

wherein the elongate metal film portions are spaced from one another in a first direction,

wherein the first wiring portions are spaced from one another in the first direction,

wherein the second wiring portions are spaced from one another in the first direction, and

wherein the first wiring portions and the second wiring portions extend in a second direction perpendicular to the first direction.