On-die termination device to compensate for a change in an external voltage

• US 7,688,104 B2
• Filed: 07/02/2008
• Issued: 03/30/2010
• Est. Priority Date: 07/03/2007
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Park, Jung Hoon
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US12/166,539
• Publication Number:
  US 20090015290A1
• Time in Patent Office: 636 Days
• Field of Search: 326/30, 326/26, 326/21, 327/108
• US Class Current: 326/30
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters

Abstract

An on-die termination (ODT) control in a semiconductor memory device compensates for a change in an external voltage. The on-die termination device includes a voltage comparator that compares an external voltage to a set internal reference voltage. The compared values are sent to a controller that controls an on-die termination impedance value according to the output signal from the voltage comparator. Based on the output of the controller, the present invention spontaneously controls an on-die termination resistance value according to the change in the external voltage without degrading device characteristics during high-speed operation.

Claims

1. An on-die termination device, comprising:

a voltage comparator comparing an external voltage and a set internal reference voltage to provide an output signal; and

a controller controlling an on-die termination impedance value according to the output signal from the voltage comparator,

wherein the controller performs a control process that makes the on-die termination impedance value small when the external voltage is higher than the reference voltage and a control process that makes the on-die termination impedance value large when the external voltage is lower than the reference voltage.

2. The on-die termination device as set forth in claim 1, wherein the voltage comparator outputs a high-level signal when the external voltage is higher than the reference voltage and outputs a low-level signal when the external voltage is lower than the reference voltage.

3. The on-die termination device as set forth in claim 1, wherein the voltage comparator comprises:

a first comparator that compares the external voltage and a first reference voltage and outputs a signal; and

a second comparator that compares the external voltage and a second reference voltage and outputs a signal.

4. The on-die termination device as set forth in claim 3, wherein the first comparator outputs a high-level signal when the external voltage is higher than the first reference voltage and outputs a low-level signal when the external voltage is lower than the first reference voltage.

5. The on-die termination device as set forth in claim 3, wherein the second comparator outputs a high-level signal when the external voltage is higher than the second reference voltage and outputs a low-level signal when the external voltage is lower than the second reference voltage.

6. The on-die termination device as set forth in claim 3, wherein the controller combines the output signals from the first comparator and the second comparator and on-die termination signals generated by external instructions to control a pull-up impedance and a pull-down impedance of the on-die termination impedance value.

7. The on-die termination device as set forth in claim 3, wherein the controller performs a control process that turns-off all switching transistors for a pull-up impedance and a pull-down impedance of the on-die termination impedance value when the external voltage is higher than the first reference voltage and the second reference voltage.

8. The on-die termination device as set forth in claim 3, wherein the controller performs a control process that turns-off all switching transistors for a pull-up impedance and a pull-down impedance of the on-die termination impedance value when the external voltage is lower than the first reference voltage and the second reference voltage.

9. The on-die termination device as set forth in claim 3, wherein the controller performs a control process that turns-on some of a plurality of switching transistors for a pull-up impedance and a pull-down impedance of the on-die termination impedance value and turns-off the remaining plurality of switching transistors when the external voltage has a value between the first reference voltage and the second reference voltage.

10. An on-die termination device, comprising:

a voltage comparator comparing an external voltage and a reference voltage to provide an output signal;

an on-die termination impedance generated by an impedance unit having a plurality of MOS transistors and a plurality of passive resistor elements; and

a controller controlling the on-die termination impedance according to the output signal from the voltage comparator,

wherein the controller performs a control process that makes the on-die termination impedance value small when the external voltage is higher than the reference voltage and a control process that makes the on-die termination impedance value large when the external voltage is lower than the reference voltage.

11. The on-die termination device as set forth in claim 10, wherein the voltage comparator comprises:

a first comparator that compares the external voltage and a first reference voltage and outputs a signal; and

a second comparator that compares the external voltage and a second reference voltage and outputs a signal.

12. The on-die termination device as set forth in claim 11, wherein the controller combines the outputs of the first comparator and the second comparator and on-die termination activation signals to turn-on/turn-off the transistors for the on-die termination impedance unit, thereby controlling the on-die termination impedance.

13. The on-die termination device as set forth in claim 11, wherein the controller comprises:

a first arithmetic unit that logically combines on-die termination activation signals and the output signals from the first comparator and the second comparator and outputs a signal;

a second arithmetic unit that logically combines the on-die termination activation signals and the output signals from the first comparator and the second comparator and outputs a signal;

a first inverter that outputs the inverse of the output signal from the first arithmetic unit;

a second inverter that outputs the inverse of the output signal from the second arithmetic unit; and

a third inverter that outputs the inverse of the on-die termination activation signals.

14. The on-die termination device as set forth in claim 13, wherein the first arithmetic unit comprises:

a first NAND arithmetic unit that uses the output signals from the first comparator and the second comparator as inputs; and

a first NOR arithmetic unit that uses the output signal from the first NAND arithmetic unit and the inverted on-die termination activation signals as inputs.

15. The on-die termination device as set forth in claim 13, wherein the second arithmetic unit comprises:

a second NOR arithmetic unit that uses the output signals from the first comparator and the second comparator as inputs; and

a second NAND arithmetic unit that uses the on-die termination activation signals and the output signal from the second NOR arithmetic unit as inputs.

16. The on-die termination device as set forth in claim 13, wherein the output signal from the first arithmetic unit is inputted to any one of a plurality of PMOS transistors for a pull-up impedance as a first pull-up signal, the output signal from the second arithmetic unit is inputted to any one of the remaining PMOS transistors for the pull-up impedance as a second pull-up signal, and the output from the third inverter is inputted to the remaining PMOS transistors for the pull-up impedance.

17. The on-die termination device as set forth in claim 13, wherein the output from the first inverter is inputted to any one of a plurality of NMOS transistors for a pull-down impedance as a first pull-down signal, the output from the second inverter is inputted to any one of the remaining NMOS transistors for the pull-down impedance as a second pull-down signal, and the on-die termination activation signals are inputted to the remaining NMOS transistors for the pull-down impedance.