Image pickup apparatus

• US 7,688,365 B2
• Filed: 10/04/2004
• Issued: 03/30/2010
• Est. Priority Date: 02/29/2000
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Inui, Fumihiro
• Primary Examiner(s): Tran; Nhan T
• Assistant Examiner(s): DIEP, TRUNG T
• Application Number:
  US10/958,056
• Publication Number:
  US 20050046719A1
• Time in Patent Office: 2,003 Days
• Field of Search: 348/241, 348/307, 348/250, 348/308
• US Class Current: 348/241
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/633 by using optical black pixels
• CPC Class Codes: H04N 25/67 applied to fixed-pattern noise, e.g. non-uniformity of response
• CPC Class Codes: H04N 25/672 between adjacent sensors or output registers for reading a single image
• CPC Class Codes: H04N 25/767 Horizontal readout lines, multiplexers or registers
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

There is provided an image pickup apparatus comprising two-dimensionally arrayed pixels, a plurality of read-out channels each including a read-out circuit and an amplifier circuit, a parallel-serial conversion circuit which sequentially selects pixel signals output via the plurality of read-out channels and outputs a series of pixel signals, and a clamp unit which clamps the reset level included in an output signal from the read-out circuit in order to remove an offset generated in each read-out channel.

Claims

1. An image pickup apparatus comprising:

a pixel area which includes a plurality of pixels arranged two-dimensionally;

first and second read-out circuits for reading out signals from the plurality of pixels, each of said first and second read-out circuits including a memory for holding signals from pixels of at least one line and a scanning circuit for reading out sequentially the signals of one line, held in said memory, and outputting the read-out signal and a reset signal alternately;

a first amplifier for inputting alternately the reset signal from said first read-out circuit and the light signal from the same and amplifying the input signals to be output;

a second amplifier for inputting alternately the reset signal from said second read-out circuit and the light signal from the same and amplifying the input signals to be output;

an offset suppressing circuit comprising first and second clamp units corresponding respectively to said first and second amplifiers for correcting the light signals by using the reset signal to suppress offsets caused by said first and second amplifiers;

first and second output terminals for reading out in parallel the signals from the first and second clamp units;

a third output terminal for reading out serially the signals from the first and second clamp units; and

a multiplexer for multiplexing the signal from said first clamp unit and the signal from said second clamp unit to said third terminal.

2. An apparatus according to claim 1, wherein said pixel area is formed so that lines of the plurality of pixels are read out alternately to said first and second read-out circuits.

3. An apparatus according to claim 1, further comprising a lens for focusing light onto the plurality of pixels and a signal processing circuit for processing the signals from said first and second amplifiers.