Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory

• US 7,688,621 B2
• Filed: 12/03/2007
• Issued: 03/30/2010
• Est. Priority Date: 06/03/2003
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Beak-hyung, Oh, Hyung-rok, Cho, Woo-yeong
• Primary Examiner(s): DINH, SON T
• Application Number:
  US11/949,299
• Publication Number:
  US 20090059658A1
• Time in Patent Office: 848 Days
• Field of Search: 365/163, 365/189.16, 365/233, 365/189.07
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

Claims

1. A hand held system, comprising:

a memory device including an array of nonvolatile memory cells and a writing driver circuit for driving at least one of the nonvolatile memory cell; and

a controller configured to be coupled to the memory device to control the memory device,

wherein the writing driver circuit includes;

a pulse selection circuit configured to output a selected one of a reset pulse and a set pulse in response to a logic level of data and the data;

a current control circuit configured to receive a bias voltage, to output a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and to output the control signal at a first level during an enable duration of the set pulse when the data is at a second level; and

a current drive circuit configured to output writing current to the at least one of the nonvolatile memory cell in response to the control signal during the enable duration of the reset pulse or of the set pulse.

2. The hand held system of claim 1, wherein the nonvolatile memory cell are a variable resistive memory (VRM) cells.

3. The hand held system of claim 1, wherein the hand held system is a SIM card for cellular telephones.

4. The hand held system of claim 1, wherein the hand held system is one of a SIMM card a DIMM card.

5. The hand held system of claim 1, wherein the hand held system is one of a chip card, a smart card and an ID card.

6. The hand held system of claim 1, wherein the hand held system is a removable memory earn such as MMC Card, a SD memory card, a multiuse card, a compact SD card, a mini SD card, a micro SD card, a memory stock and a USB device.

7. The hand held system of claim 1, wherein the memory device consists essentially of integrated circuits and metallization on an integrated circuit die.

8. The hand held system of claim 1, wherein the controller includes a buffer memory and performs control of the memory device through a data bus and an address bus.

9. A high capacity storage system, comprising:

a memory device including an array of nonvolatile memory cells and a writing driver circuit for driving at least one of the nonvolatile memory cells; and

a controller configured to be coupled to the memory device to control the memory device,

wherein the motion driver circuit includes;

a pulse selection circuit configured to output a selected one of a reset pulse and a set pulse in response to a logic level of data and the data;

a current control circuit configured to receive a bias voltage, to output a control signal at a second level during an enable duration of the reset pulse when the data is at first level, and to output the control signal at a first level during an enable duration of the set pulse when the data is at a second level; and

a current drive circuit configured to output writing current to the at least one of the nonvolatile memory cells in response to the control signal during the enable duration of the reset pulse or of the set pulse.

10. The high capacity storage system of claim 9, wherein the nonvolatile memory cells are variable resistive memory (VRM) cells.

11. The high capacity storage system of claim 9, wherein the high capacity storage system is a Solid State Disk (SSD).

12. The high capacity storage system of claim 9, wherein the high capacity storage system is one of a Hybrid Disk Drive (HDD) and a Hybrid RAID Drive (HRD).

13. The high capacity storage system of claim 9, further comprising:

a hard disk; and

a hard disk controller configured to coupled to the hard disk to control the hard disk,

wherein the memory device serves as a buffer memory.

14. The high capacity storage system of claim 9, further comprising:

a CPU configured to be coupled to the controller to access the memory device.

15. The high capacity storage system of claim 14, wherein the high capacity storage system is implemented as one of a personal computer system, a digital camera system, a scanner, a machine vision system, a vehicle navigation system, a cellular phone, an auto focus system, a star tracker system, a surveillance system, a motion detection system, an image stabilization system for digital cameras and a data compression system for high-definition television.

16. A multi-chip package, comprising:

a first integrated circuit die including a logic circuit; and

at least one second integrated circuit die including an array of nonvolatile memory cells and a writing driver circuit for driving at least one of the nonvolatile memory cells, the writing driving circuit including;

a pulse selection circuit configured to output a selected one of a reset pulse and a set pulse in response to a logic level of data and the data;

a current control circuit configured to receive a bias voltage, to output a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and to output the control signal at a first level during an enable duration of the set pulse when the data is at a second level; and

a current drive circuit configured to output writing current to the nonvolatile memory cell in response to the control signal during the enable duration of the reset pulse or of the set pulse.

17. The multi-chip package of claim 16, wherein the nonvolatile memory cells are variable resistive memory (VRM) cells.

18. The multi-chip package of claim 16, wherein the logic circuit is a CPU.

19. The multi-chip package of claim 16, further comprising an interspersed insulating adhesive layers disposed between each adjacent pair of the first and the at least one second integrated circuit die.

20. The multi-chip package of claim 19, further comprising an insulating substrate,

wherein the first integrated circuit die, the at least one second integrated circuit die and the interspersed insulation adhesive layers are mounted on the insulating substrate.