Semiconductor memory device, and method of controlling the same
First Claim
1. A semiconductor device comprising:
- a memory core with a plurality of memory cells;
an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line;
a command decoder that receives a plurality of control signals and generates an internal command signal; and
a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, andwherein the internal voltage generator includes a reference voltage generator, a detector and a booster circuit.
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Accused Products
Abstract
An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.
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Citations
25 Claims
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1. A semiconductor device comprising:
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a memory core with a plurality of memory cells; an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line; a command decoder that receives a plurality of control signals and generates an internal command signal; and a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and wherein the internal voltage generator includes a reference voltage generator, a detector and a booster circuit. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a memory core with a plurality of memory cells; an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage the memory core via the internal power supply line; a command decoder that receives a plurality of control signals and generates an internal command signal; and a low power entry circuit, coupled to the command decoder, that receives at least on of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator includes a plurality of booster circuits, coupled to the low power entry circuit, and at least one of the plurality of booster circuits is inactivated in response to the low power signal, and wherein the internal voltage generator includes a reference voltage generator and a detector. - View Dependent Claims (8, 9)
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10. A semiconductor device comprising:
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a memory core with a plurality of memory cells; an internal voltage generator, coupled to the memory core via an internal power supply line, that generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line in a normal mode; a command decoder that receives a plurality of control signals and generates an internal command signal; and a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein a voltage, which is lower than the boosted internal voltage, is supplied to the internal power supply line in the low power consumption mode, and wherein the internal voltage generator includes a reference voltage generator and a detector.
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11. A semiconductor device comprising:
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a memory core including a plurality of memory cells; an internal voltage generator, coupled to the memory core via an internal power supply line, that generates an internal voltage based on an external voltage and supplies the internal voltage to the memory core via the internal power supply line; a command decoder that receives a plurality of control signals and generates an internal command signal; and a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and wherein the internal voltage generator includes a reference voltage generator, a comparator, a compensating circuit and a regulator. - View Dependent Claims (12, 13, 14, 15)
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16. A semiconductor device provided on a substrate comprising:
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an internal voltage generator that generates an internal voltage based on an external voltage and supplies the internal voltage to the substrate via an internal power supply line; a command decoder that receives a plurality of control signals and generates an internal command signal; and a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and wherein the internal voltage generator includes an oscillator and a pumping circuit. - View Dependent Claims (17, 18, 19, 20)
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21. A semiconductor device comprising:
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a bit line coupled to a memory cell; an internal voltage generator that generates an internal voltage based on an external voltage and supplies the internal voltage to precharge the bit line; a command decoder that receives a plurality of control signals and generates an internal command signal; and a low power entry circuit, coupled to the command decoder, that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited, wherein the internal voltage generator, coupled to the low power entry circuit, stops supplying the internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device, and wherein the internal voltage generator includes a reference voltage generator and a comparator. - View Dependent Claims (22, 23, 24, 25)
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Specification