System and method for automatically updating the memory map of a programmable controller to customized hardware

• US 7,689,727 B2
• Filed: 06/28/2006
• Issued: 03/30/2010
• Est. Priority Date: 01/24/2006
• Status: Active Grant

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Chandhoke, Sundeep
• Primary Examiner(s): Patel; Niketa I
• Assistant Examiner(s): Abad; Farley J
• Application Number:
  US11/427,052
• Publication Number:
  US 20070174518A1
• Time in Patent Office: 1,371 Days
• Field of Search: 710/2, 710/8, 710/10, 710/15, 700/40
• US Class Current: 710/8
• CPC Class Codes: G05B 19/054 Input/output
• CPC Class Codes: G05B 2219/1107 Hardware expansion of function of plc, programmable, connected in output line

Abstract

System and method for automatically updating a memory map coupled to or included in a programmable controller (PrC). A PrC may automatically detect at least one programmable hardware element (PHE) coupled to the PrC. The PHE may provide a customizable interface, i.e., input and output (I/O) interface, between one or more devices and the PrC. The devices may include one or more measurement, data acquisition, signal generation, automation, motion control, and/or analysis device(s), among others. The PHE may perform one or more functions on the data transmitted between the device(s) and the PrC. One or more of the PHEs and/or device(s) may be local or remote to the PrC. The PrC may automatically update the memory map based on a hardware I/O interface of the at least one programmable hardware element, where the memory map facilitates communications between programs executing on the PrC and the programmable hardware element.

Claims

1. A method, comprising:

a programmable controller automatically detecting at least one programmable hardware element (PHE) coupled to the programmable controller, wherein the at least one PHE comprises a programmable logic device (PLD);

the programmable controller automatically updating a memory map based on a hardware I/O interface of the at least one PHE, wherein the memory map facilitates communications between programs executing on the programmable controller and the at least one PHE, and wherein the at least one PHE provides a customizable interface between one or more devices and the programs executing on the programmable controller; and

the programmable controller retrieving and storing information from and to the memory map a plurality of times to update information to and from the at least one PHE, wherein said retrieving and storing comprises the programmable controller utilizing a scanning architecture.

2. The method of claim 1, wherein said retrieving and storing information from and to the memory map is performed cyclically and comprises:

the programmable controller retrieving first information from the memory map and providing the first information to programs executing on the programmable controller; and

the programmable controller retrieving second information from the programs executing on the programmable controller and providing the second information in the memory map.

3. The method of claim 1,

wherein the programmable controller comprises a programmable logic controller.

4. The method of claim 1,

wherein the programmable controller comprises a programmable automation controller.

5. The method of claim 1,

wherein the programmable controller comprises a distributed controller system.

6. The method of claim 1, further comprising:

executing at least one program on the programmable controller, wherein the at least one program operates in conjunction with the at least one PHE, and wherein the at least one program is comprised in a task executing on the programmable controller.

7. The method of claim 6,

wherein the at least one program comprises one or more of:

at least one graphical program, wherein the at least one graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program; and

at least one text-based program.

8. The method of claim 1, further comprising:

receiving at least one program to the programmable controller from a host computer system coupled to the programmable controller; and

executing the at least one program, wherein the at least one program operates in conjunction with the at least one PHE, and wherein the at least one program is comprised in a task executing on the programmable controller.

9. The method of claim 1, wherein the at least one PHE comprises at least one field-programmable gate array (FPGA).

10. The method of claim 1, wherein the programmable controller is comprised in a chassis, wherein the chassis comprises one or more slots, wherein at least one of the one or more devices comprises a module inserted into a slot of the chassis.

11. The method of claim 1, wherein the at least one PHE is comprised within the backplane of the chassis.

12. The method of claim 1, wherein the one or more devices comprise one or more of:

a measurement device;

a data acquisition device;

a signal generation device;

an automation device;

a motion control device; and

an analysis device.

13. The method of claim 1, further comprising:

the at least one PHE receiving data from at least one device of the one or more devices coupled to the at least one PHE;

the at least one PHE performing one or more functions on the data, thereby generating modified data; and

the at least one PHE providing the modified data to the programmable controller.

14. The method of claim 1, further comprising:

the at least one PHE receiving data from the programmable controller;

the at least one PHE performing one or more functions on the data, thereby generating modified data; and

the at least one PHE providing the modified data to at least one device of the one or more devices coupled to the at least one PHE.

15. The method of claim 1, wherein the at least one PHE is located remotely from the programmable controller.

16. The method of claim 1,

wherein the at least one PHE comprises a plurality of PHEs coupled to the programmable controller, wherein at least one of the plurality of PHEs is located remotely from the programmable controller.

17. The method of claim 1, further comprising:

halting the programmable controller in response to received input;

automatically detecting a new hardware I/O interface of the at least one PHE; and

automatically updating the memory map according to the new hardware I/O interface of the at least one PHE;

wherein said halting, said automatically detecting the new hardware I/O interface, and said automatically updating the memory map according to the new hardware I/O interface is performed one or more times.

18. The method of claim 17,

wherein the received input comprises input received from one or more of:

a computer system coupled to the programmable controller;

a user via the computer system coupled to the programmable controller;

a controller module coupled to the programmable controller;

a device coupled to the programmable controller; and

a user.

19. The method of claim 1,

wherein the programmable controller comprises a soft programmable controller executing on a host computer.

20. The method of claim 1,

wherein the programmable controller is specified by a first portion of a graphical program and the PHE is specified by a second portion of the graphical program, and wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program.

21. The method of claim 1, further comprising:

receiving input invoking said automatic detection and said automatic updating.

22. The method of claim 1,

wherein said automatic detection and said automatic updating are performed during initialization of the programmable controller.

23. The method of claim 1, further comprising:

the programmable controller automatically detecting a new hardware interface of the at least one PHE; and

the programmable controller automatically updating the memory map based on the new hardware interface of the at least one PHE.

24. A programmable controller, comprising:

a processor;

a memory medium coupled to the processor, comprising program instructions executable by the processor to;

automatically detect at least one programmable hardware element (PHE) coupled to the programmable controller, wherein the at least one PHE provides a customizable interface between one or more devices and one or more programs executing on the programmable controller, and wherein the at least one PHE comprises a programmable logic device (PLD);

automatically update a memory map based on a hardware I/O interface of the at least one programmable hardware element, wherein the memory map facilitates communications between the one or more programs executing on the programmable controller and the at least one PHE; and

retrieve and store information from and to the memory map a plurality of times to update information to and from the at least one PHE, wherein said retrieving and storing comprises the programmable controller utilizing a scanning architecture.

25. A computer-accessible memory medium comprising program instructions, wherein the program instructions are executable by a processor to:

automatically detect at least one programmable hardware element (PHE) coupled to a programmable controller, wherein the at least one PHE provides a customizable interface between one or more devices and one or more programs executing on the programmable controller, wherein the at least one PHE comprises a programmable logic device (PLD);

automatically update a memory map based on a hardware I/O interface of the at least one programmable hardware element, wherein the memory map facilitates communications between the one or more programs executing on the programmable controller and the at least one PHE; and

retrieve and store information from and to the memory map a plurality of times to update information to and from the at least one PHE, wherein said retrieving and storing comprises the programmable controller utilizing a scanning architecture.

26. A system, comprising:

means for automatically detecting at least one programmable hardware element (PHE) coupled to a programmable controller, wherein the at least one PHE provides a customizable interface between one or more devices and one or more programs executing on the programmable controller wherein the at least one PHE comprises a programmable logic device (PLD);

means for automatically updating a memory map based on a hardware I/O interface of the at least one PHE, wherein the memory map facilitates communications between the one or more programs executing on the programmable controller and the at least one PHE; and

means for retrieving and storing information from and to the memory map a plurality of times to update information to and from the at least one PHE, wherein said retrieving and storing comprises the programmable controller utilizing a scanning architecture.