System and method for on-board timing margin testing of memory modules

• US 7,689,879 B2
• Filed: 05/09/2006
• Issued: 03/30/2010
• Est. Priority Date: 09/12/2003
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Primary Examiner(s): BRITT, CYNTHIA H
• Application Number:
  US11/431,437
• Publication Number:
  US 20060206761A1
• Time in Patent Office: 1,421 Days
• Field of Search: 714/715, 714/718, 714/719, 714/742, 365200-201
• US Class Current: 714/718
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G11C 2029/3602 Pattern generator
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a self-test module. The self-test module includes a pattern generator producing write data having a predetermined pattern, and a flip-flop having a data input receiving the write data. A clock input of the flip-flop receives an internal clock signal from a delay line that receives a variable frequency clock generator. Read data are coupled from the memory devices and their pattern compared to the write data pattern. The delay of the delay line and frequency of the clock signal can be varied to test the speed margins of the memory devices.

Claims

1. A memory module, comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface for receiving memory requests for access to at least one of the memory devices;

a self-test module coupled to the at least one memory device, the self-test module operable to generate a test signal based on a test parameter, the self-test module operable to transmit the test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, the self-test module comprising a maintenance bus interface operable to receive the test parameter and transmit the test result; and

a first bus coupled between the memory module and the at least one memory device.

2. The memory module of claim 1 further comprising a maintenance bus coupled to the maintenance bus interface.

3. The memory module of claim 1 wherein the memory devices comprises a plurality of synchronous dynamic random access memory devices.

4. A memory module comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface for receiving memory requests for access to at least one of the memory devices;

a self-test module coupled to the at least one memory device, the self-test module operable to transmit a test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, the test result comprising a frequency at which the at least one memory device operates correctly; and

a first bus coupled between the memory module and the at least one memory device.

5. A memory module comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface for receiving memory requests for access to at least one of the memory devices;

a self-test module coupled to the at least one memory device, the self-test module operable to transmit a test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, the test result comprising a timing skew at which the at least one memory device operates correctly; and

a first bus coupled between the memory module and the at least one memory device.

6. A memory module comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface for receiving memory requests for access to at least one of the memory devices;

a self-test module coupled to the at least one memory device the self-test module operable to transmit a test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, wherein the test signal is not carried on a bus other than the first bus; and

a first bus coupled between the memory module and the at least one memory device.

7. A memory module comprising:

a plurality of memory devices; and

a memory hub, comprising;

a link interface for receiving memory requests for access to at least one of the memory devices;

a self-test module coupled to the at least one memory device, the self-test module operable to transmit a test signal comprising a series of corresponding first and second signals to the at least one of memory devices, wherein transmitting the test signal comprises coupling the series of corresponding first and second signals to the at least one memory device and altering the relative timing between when some of the corresponding first and second signals in the series are coupled to the at least one memory device, the self-test mode further operable to receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal; and

a first bus coupled between the memory module and the at least one memory device.

8. The memory module of claim 7, the responsive signal comprising output signals from the at least one memory device, the self-test module determining, based on the received output signals, whether the at least one memory device properly responded to the series of first and second signals.

9. The memory module of claim 8 wherein the self-test module further comprises:

a pattern generator producing a pattern of data bits each of which is used to generate a respective one the first signals in the series; and

a comparator coupled to the pattern generator and to the at least one memory device, the comparator receiving output signals from the at least one memory device and determining a pattern of data corresponding thereto, the comparator further comparing the pattern generated from the output signals to the pattern of data from which the first signals are generated.

10. The memory module of claim 9 wherein the self-test module further comprises a storage device coupled to the comparator to store the results of the comparisons between the pattern generated from the output signals and the pattern of data from which the first signals are generated.

11. The memory module of claim 8 wherein the self-test module comprises:

a delay line receiving a clock signal that is synchronized to the second signals in the series, the delay line being operable to generate from the clock signal a respective internal clock signal that is used to control the timing of when each of the first signals in the series is coupled to the at least one memory device;

a memory sequencer coupled to the at least one memory device, the memory sequencer being operable to generate and couple to at least one memory device a sequence of control signals to cause the at least one memory device to respond to each of the first and second signals in the series; and

a built-in self-test engine coupled to the delay line and to the memory sequencer operable to control the delay of the delay line.

12. The memory module of claim 11 wherein the self-test module further comprises a flip-flop having a data input receiving each of the first signals in the series, a clock input receiving the internal clock signal, and an output coupled to the at least one memory device.

13. The memory module of claim 11 wherein each of the first signals comprises a data signal and each of the second signals comprise a data strobe signal.

14. The memory module of claim 11 wherein the self-test module is further operable to couple a signal from the memory device corresponding to each of the output signals and to alter the relative timing between the signal coupled from the at least one memory device and the corresponding output signal.

15. A memory module comprising:

a plurality of memory devices; and

a memory hub comprising;

a link interface for receiving memory requests for access to at least one of the memory devices;

a clock generator operable to produce and couple to the at least one memory device a clock signal having a frequency;

a self-test module coupled to the at least one memory device and the clock generator, the self-test module operable to transmit a test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, the self-test module being further operable to vary the frequency of the clock signal over a range, the test signal comprising a series of first input signals and the responsive signal comprising a respective series of output signals from the at least one memory device, and the test result comprising an indicator of whether the at least one memory device properly responded to the series of first signals as the frequency of the clock signal is varied; and

a first bus coupled between the memory module and the at least one memory device.

16. The memory module of claim 15, wherein the self-test module further comprises:

a delay line coupled to receive the clock signal from the clock generator and being operable to generate a delayed internal clock signal; and

a flip-flop having a data input coupled to receive the first signal, a clock input coupled to receive the internal clock signal, and an output coupled to the at least one memory device.

17. A processor-based system, comprising:

a processor having a processor bus;

a system controller coupled to the processor bus, the system controller having a system memory port and a peripheral device port; and

a memory module coupled to the system memory port of the system controller, the memory module comprising;

a plurality of memory devices; and

a memory hub, comprising;

a link interface for receiving memory requests for access to at least one of the memory devices;

a self-test module coupled to the at least one memory device, the self-test module operable to transmit a test signal to the at least one of memory devices on a first bus receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal; and

a second bus coupled between the memory hub and the at least one memory device, the second bus being different from the first bus.

18. The processor-based system of claim 17 wherein the self-test module generates the test signal based on a test parameter, the self-test module further comprising:

a maintenance bus interface operable to receive the test parameter and transmit the test result.

19. The processor-based system of claim 18 wherein the first bus is a maintenance bus and is coupled to the maintenance bus interface.

20. The processor-based system of claim 17 wherein the test result comprises a frequency at which the at least one memory device operates correctly.

21. The processor-based system of claim 17 wherein the test result comprises a timing skew at which the at least one memory device operates correctly.

22. The processor-based system of claim 17 wherein the test signal comprises a series of corresponding first and second signals, the self-test module being operable to couple the series of corresponding first and second signals to the at least one memory device and to alter the relative timing between when some of the corresponding first and second signals in the series are coupled to the at least one memory device.

23. The processor-based system of claim 22, the responsive signal comprising output signals from the at least one memory device, the self-test module determining, based on the received output signals, whether the at least one memory device properly responded to the series of first and second signals.

24. The processor-based system of claim 23 wherein the self-test module further comprises:

a pattern generator producing a pattern of data bits each of which is used to generate a respective one the first signals in the series; and

a comparator coupled to the pattern generator and to the at least one memory device, the comparator receiving output signals from the at least one memory device and determining a pattern of data corresponding thereto, the comparator further and comparing the pattern generated from the output signals to the pattern of data from which the first signals are generated.

25. The processor-based system of claim 24 wherein the self-test module further comprises a storage device coupled to the comparator to store the results of the comparisons between the pattern generated from the output signals and the pattern of data from which the first signals are generated.

26. The processor-based system of claim 23 wherein the self-test module comprises:

a delay line receiving a clock signal that is synchronized to the second signals in the series, the delay line being operable to generate from the clock signal a respective internal clock signal that is used to control the timing of when each of the first signals in the series is coupled to the at least one memory device;

a memory sequencer coupled to the at least one memory device, the memory sequencer being operable to generate and couple to at least one memory device a sequence of control signals to cause the at least one memory device to respond to each of the first and second signals in the series; and

a built-in self-test engine coupled to the delay line and to the memory sequencer operable to control the delay of the delay line.

27. The processor-based system of claim 26 wherein the self-test module further comprises a flip-flop having a data input receiving each of the first signals in the series, a clock input receiving the internal clock signal, and an output coupled to the at least one memory device.

28. The processor-based system of claim 26 wherein each of the first signals comprises a data signal and each of the second signals comprise a data strobe signal.

29. The processor-based system of claim 26 wherein the self-test module is further operable to couple a signal from the memory device corresponding to each of the output signals and to alter the relative timing between the signal coupled from the at least one memory device and the corresponding output signal.

30. The processor-based system of claim 17 wherein the memory devices comprises a plurality of synchronous dynamic random access memory devices.

31. The processor-based system of claim 17, the memory hub further comprising:

a clock generator operable to produce and couple to the at least one memory device a clock signal having a frequency; and

the self-test module coupled to the clock generator, the self-test module being further operable to vary the frequency of the clock signal over a range, the test signal comprising a series of first input signals and the responsive signal comprising a respective series of output signals from the at least one memory device, and the test result comprising an indicator of whether the at least one memory device properly responded to the series of first signals as the frequency of the clock signal is varied.

32. The memory module of claim 31, wherein the self-test module further comprises:

a delay line coupled to receive the clock signal from the clock generator and being operable to generate a delayed internal clock signal; and

a flip-flop having a data input coupled to receive the first signal, a clock input coupled to receive the internal clock signal, and an output coupled to the at least one memory device.

33. A method for testing in a memory system having a memory hub coupled to a plurality of memory devices, the method comprising:

generating testing signals in the memory hub;

coupling the testing signals from the memory hub to the memory devices and varying the relative timing between when the test signals are applied to the memory devices;

generating output signals in the memory devices resulting from the testing signals;

coupling the output signals from the memory devices to the memory hub; and

evaluating the output signals in the memory hub to determine if the memory devices properly responded to the test signals.

34. The method of claim 33 wherein the testing signals comprise data signals and corresponding data strobe signals.

35. The method of claim 34 wherein the act of generating testing signals in the memory hub comprises:

generating a pattern of data;

storing the pattern of data; and

producing write data bit signals from the data pattern.

36. The method of claim 35 wherein the act of generating output signals in the memory devices resulting from the testing signals comprise generating read data bit signals.

37. The method of claim 36 wherein the act of evaluating the output signals in the memory hub comprises:

determining a data pattern corresponding to the read data bit signals received from the memory devices; and

comparing the data pattern corresponding to the read data bit signals to the stored pattern of data.

38. The method of claim 33 wherein the testing signals comprise a command signal and a clock signal.

39. The method of claim 38 wherein the act of coupling the testing signals to the memory devices comprises coupling the command and the clock signal to at least one memory device while altering the relative timing between the command and the clock signal.

40. The method of claim 33 wherein the test signals comprise write data signals.

41. The method of claim 33 wherein the test signals comprise command signals.

42. A method for testing in a memory system having a memory hub coupled to a plurality of memory devices, the method comprising:

generating testing signals in the memory hub, wherein the testing signals comprise a clock signal having a variable frequency;

altering the frequency of the clock signal;

coupling the testing signals from the memory hub to the memory devices responsive to the clock signal;

generating output signals in the memory devices resulting from the testing signals;

coupling the output signals from the memory devices to the memory hub; and

evaluating the output signals in the memory hub to determine if the memory devices properly responded to the test signals.

43. A memory, comprising:

at least one memory device; and

a memory hub coupled to the at least one memory device, the memory hub including a self-test module configured to generate a plurality of test signals, transmit the plurality of test signals to the at least one memory device, alter at least one of a timing or a rate at which at least one of the plurality of test signals are transmitted to the at least one memory device relative to the other of the plurality of test signals, receive a plurality of responsive signals from the at least one memory device, and compare the plurality of generated test signals with the plurality of responsive signals to determine whether the at least one memory device is operating properly.

44. The memory of claim 43 wherein the memory hub further comprises a bus configured coupled to the self-test module and configured to be coupled to an external device.

45. The memory of claim 43 wherein the self-test mode comprises a pattern generator to configured to generate the plurality of test signal and a comparator to configured to compare the plurality of generated test signals with the plurality of responsive signals.

46. The memory of claim 43 wherein the self-test module further includes a clock generator configured to generate a clock signal having a frequency, the self-test module configured to vary the frequency of the clock signal over a range as the plurality of test signals are transmitted to the at least one memory device.