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System and method for on-board timing margin testing of memory modules

  • US 7,689,879 B2
  • Filed: 05/09/2006
  • Issued: 03/30/2010
  • Est. Priority Date: 09/12/2003
  • Status: Expired due to Fees
First Claim
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1. A memory module, comprising:

  • a plurality of memory devices; and

    a memory hub, comprising;

    a link interface for receiving memory requests for access to at least one of the memory devices;

    a self-test module coupled to the at least one memory device, the self-test module operable to generate a test signal based on a test parameter, the self-test module operable to transmit the test signal to the at least one of memory devices, receive a responsive signal from the at least one memory device, and determine a test result indicative of whether the at least one memory device responded correctly to the test signal, the self-test module comprising a maintenance bus interface operable to receive the test parameter and transmit the test result; and

    a first bus coupled between the memory module and the at least one memory device.

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