Central processor for a camera with printing capabilities
First Claim
1. A central processor for a camera having printing capabilities, the central processor comprisinga CPU core;
- a data cache connected to the core;
a vector processor connected to the core via the data cache;
a RAM interface connected to the data cache to permit communication with a RAM;
an input buffer connected to the processor;
an image sensor interface connected to the input buffer for communication with the processor;
a card reader interface connected to the input buffer for communication with the processor;
an output buffer connected to the processor; and
a printhead interface connected to the output buffer for communication with the processor.
1 Assignment
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Accused Products
Abstract
A central processor for a camera having printing capabilities has a CPU core. A data cache is connected to the core. A vector processor is connected to the core via the data cache. A RAM interface is connected to the data cache to permit communication with a RAM. An input buffer is connected to the processor. An image sensor interface is connected to the input buffer for communication with the processor. A card reader interface is connected to the input buffer for communication with the processor. An output buffer is connected to the processor. A printhead interface is connected to the output buffer for communication with the processor.
89 Citations
9 Claims
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1. A central processor for a camera having printing capabilities, the central processor comprising
a CPU core; -
a data cache connected to the core; a vector processor connected to the core via the data cache; a RAM interface connected to the data cache to permit communication with a RAM; an input buffer connected to the processor; an image sensor interface connected to the input buffer for communication with the processor; a card reader interface connected to the input buffer for communication with the processor; an output buffer connected to the processor; and a printhead interface connected to the output buffer for communication with the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification