Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
First Claim
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1. A method of fabricating a semiconductor device, comprising:
- forming stress inducing layers under a first gate structure, wherein the stress inducing layers comprise;
(i) a SiGe layer formed on a first Si layer formed on a substrate and (ii) a second Si layer formed on the SiGe layer;
protecting portions of the stress inducing layers under the first gate structure;
protecting a second gate structure having a stress component associated therewith;
etching unprotected areas of the stress inducing layers at sides of the first gate structure to form openings and a resulting stress under the first gate structure, wherein the etching exposes an upper surface of the first Si layer formed on the substrate;
forming a second SiGe layer on etched portions of a silicon layer of the second gate structure;
forming a third Si layer on the second SiGe layer;
filling the openings with a material by forming a fourth Si layer on the exposed upper surface of the first Si layer; and
forming a shallow trench isolation (STI) on the substrate,wherein the stress inducing layers are formed adjacent to the STI, anda bottom surface of the STI and a bottom surface of the first Si layer are formed on an upper surface of the substrate.
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Abstract
The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.
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Citations
20 Claims
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1. A method of fabricating a semiconductor device, comprising:
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forming stress inducing layers under a first gate structure, wherein the stress inducing layers comprise;
(i) a SiGe layer formed on a first Si layer formed on a substrate and (ii) a second Si layer formed on the SiGe layer;protecting portions of the stress inducing layers under the first gate structure; protecting a second gate structure having a stress component associated therewith; etching unprotected areas of the stress inducing layers at sides of the first gate structure to form openings and a resulting stress under the first gate structure, wherein the etching exposes an upper surface of the first Si layer formed on the substrate; forming a second SiGe layer on etched portions of a silicon layer of the second gate structure; forming a third Si layer on the second SiGe layer; filling the openings with a material by forming a fourth Si layer on the exposed upper surface of the first Si layer; and forming a shallow trench isolation (STI) on the substrate, wherein the stress inducing layers are formed adjacent to the STI, and a bottom surface of the STI and a bottom surface of the first Si layer are formed on an upper surface of the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of fabricating a semiconductor device, comprising:
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forming stress inducing layers under a first gate structure, wherein the stress inducing layers comprise;
(i) a SiGe layer formed on a first Si layer formed on a substrate and (ii) a second Si layer formed on the SiGe layer;etching portions of a silicon layer associated with a second gate structure; forming a second SiGe layer on the etched portions of the silicon layer associated with the second gate structure, wherein the second SiGe layer induces a first stress in the silicon layer associated with the second gate structure; protecting the second gate structure; protecting, with sacrificial spacers, portions of the stress inducing layers; etching unprotected areas of the stress inducing layers at sides of the first gate structure to form openings, and which induces a second stress under the first gate structure, and exposes an upper surface of the first Si layer formed on the substrate; forming a third Si layer on the second SiGe layer; filling the openings with a material by forming a fourth Si layer on the exposed upper surface of the first Si layer; and forming a shallow trench isolation (STI) on the substrate, wherein the stress inducing layers are formed adjacent to the STI, and a bottom surface of the STI and a bottom surface of the first Si layer are formed on an upper surface of the substrate. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification