Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

• US 7,691,698 B2
• Filed: 02/21/2006
• Issued: 04/06/2010
• Est. Priority Date: 02/21/2006
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mocuta, Dan M., Mocuta, Anda C., Chidambarrao, Dureseti, Radens, Carl
• Primary Examiner(s): Coleman; W. David
• Assistant Examiner(s): Kim; Su C
• Application Number:
  US11/358,483
• Publication Number:
  US 20070196987A1
• Time in Patent Office: 1,505 Days
• Field of Search: 439/199, 439/142, 439/157, 439/176, 439194-195, 439/197, 439/203, 439/222, 439/283, 439/290, 439/300, 257/369, 257/E21.421, 257/E21.455, 257/E21.623, 257/E21.637, 257/371, 257/E21.611
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

Claims

1. A method of fabricating a semiconductor device, comprising:

forming stress inducing layers under a first gate structure, wherein the stress inducing layers comprise;

(i) a SiGe layer formed on a first Si layer formed on a substrate and (ii) a second Si layer formed on the SiGe layer;

protecting portions of the stress inducing layers under the first gate structure;

protecting a second gate structure having a stress component associated therewith;

etching unprotected areas of the stress inducing layers at sides of the first gate structure to form openings and a resulting stress under the first gate structure, wherein the etching exposes an upper surface of the first Si layer formed on the substrate;

forming a second SiGe layer on etched portions of a silicon layer of the second gate structure;

forming a third Si layer on the second SiGe layer;

filling the openings with a material by forming a fourth Si layer on the exposed upper surface of the first Si layer; and

forming a shallow trench isolation (STI) on the substrate,

wherein the stress inducing layers are formed adjacent to the STI, and

a bottom surface of the STI and a bottom surface of the first Si layer are formed on an upper surface of the substrate.

2. The method as claimed in claim 1, wherein the stress inducing layers comprise the SiGe layer and the second Si layer.

3. The method as claimed in claim 2, wherein the SiGe layer comprises approximately 20% Ge.

4. The method as claimed in claim 3, wherein the SiGe layer is approximately 200 Å

thick.

5. The method as claimed in claim 3, wherein the second Si layer is approximately 100 Å

thick.

6. The method as claimed in claim 1, wherein the first gate structure is used to form an NFET device and the second gate structure is used to form a PFET device.

7. The method as claimed in claim 1, further comprising forming a nitride protecting layer on the first gate structure to protect the first gate structure and portions of the stress inducing layers, and forming a liner to protect the second gate structure during the etching step and during selective epitaxial growth.

8. The method as claimed in claim 1, wherein the step of etching unprotected areas of the stress inducing layers comprises etching the SiGe layer and the second Si layer to an underlying SOI layer by reactive ion etching.

9. The method as claimed in claim 1, wherein the forming of the stress inducing layers includes forming the SiGe layer and the second Si layer, and further comprising etching the SiGe layer and the second Si layer to form a tensile stress under the first gate structure.

10. The method as claimed in claim 1, wherein the stress inducing layers and the stress component are formed on a same substrate.

11. The method as claimed in claim 1, wherein the stress inducing layers under the first gate structure are under a tensile stress, and the first gate is used for a NFET device.

12. The method as claimed in claim 1, further comprising forming sidewall spacers on the second Si layer,

wherein the etching includes removing material in an area defined by the sidewall spacers and the STI.

13. A method of fabricating a semiconductor device, comprising:

forming stress inducing layers under a first gate structure, wherein the stress inducing layers comprise;

(i) a SiGe layer formed on a first Si layer formed on a substrate and (ii) a second Si layer formed on the SiGe layer;

etching portions of a silicon layer associated with a second gate structure;

forming a second SiGe layer on the etched portions of the silicon layer associated with the second gate structure, wherein the second SiGe layer induces a first stress in the silicon layer associated with the second gate structure;

protecting the second gate structure;

protecting, with sacrificial spacers, portions of the stress inducing layers;

etching unprotected areas of the stress inducing layers at sides of the first gate structure to form openings, and which induces a second stress under the first gate structure, and exposes an upper surface of the first Si layer formed on the substrate;

forming a third Si layer on the second SiGe layer;

filling the openings with a material by forming a fourth Si layer on the exposed upper surface of the first Si layer; and

forming a shallow trench isolation (STI) on the substrate,

wherein the stress inducing layers are formed adjacent to the STI, and

a bottom surface of the STI and a bottom surface of the first Si layer are formed on an upper surface of the substrate.

14. The method as claimed in claim 13, wherein:

the SiGe layer comprises approximately 20% Ge,

the SiGe layer is approximately 200 Å

thick, and

the second Si layer is approximately 100 Å

thick.

15. The method as claimed in claim 13, wherein the first gate structure is used to form an NFET device and the second gate structure is used to form a PFET device.

16. The method as claimed in claim 13, further comprising forming a nitride protecting layer on the first gate structure to protect the first gate structure and portions of the stress inducing layers, and forming a liner to protect the second gate structure during the etching the portions of the silicon layer associated with the second gate structure step and during selective epitaxial growth.

17. The method as claimed in claim 13, wherein the step of etching unprotected areas of the stress inducing layers comprises etching the SiGe layer and the second Si layer to an underlying SOL layer by reactive ion etching.

18. The method as claimed in claim 13, wherein the forming of the stress inducing layers includes forming the SiGe layer and the second Si layer, and further comprising etching the SiGe layer and the second Si layer to form a tensile stress under the first gate structure.

19. The method as claimed in claim 13, wherein the stress inducing layers and the stress component are formed on a same substrate.

20. The method as claimed in claim 13, wherein the stress inducing layers under the first gate structure are under a tensile stress, and the first gate is used for a NFET device.