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Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

  • US 7,691,698 B2
  • Filed: 02/21/2006
  • Issued: 04/06/2010
  • Est. Priority Date: 02/21/2006
  • Status: Expired due to Fees
First Claim
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1. A method of fabricating a semiconductor device, comprising:

  • forming stress inducing layers under a first gate structure, wherein the stress inducing layers comprise;

    (i) a SiGe layer formed on a first Si layer formed on a substrate and (ii) a second Si layer formed on the SiGe layer;

    protecting portions of the stress inducing layers under the first gate structure;

    protecting a second gate structure having a stress component associated therewith;

    etching unprotected areas of the stress inducing layers at sides of the first gate structure to form openings and a resulting stress under the first gate structure, wherein the etching exposes an upper surface of the first Si layer formed on the substrate;

    forming a second SiGe layer on etched portions of a silicon layer of the second gate structure;

    forming a third Si layer on the second SiGe layer;

    filling the openings with a material by forming a fourth Si layer on the exposed upper surface of the first Si layer; and

    forming a shallow trench isolation (STI) on the substrate,wherein the stress inducing layers are formed adjacent to the STI, anda bottom surface of the STI and a bottom surface of the first Si layer are formed on an upper surface of the substrate.

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