Fabricating non-volatile memory with dual voltage select gate structure
First Claim
1. A method for fabricating a select gate structure, comprising:
- forming a first conductive portion over a substrate;
forming a dielectric portion over a first part of the first conductive portion and over the substrate;
forming a conductive layer over the first conductive portion and the dielectric portion;
etching the conductive layer to form spaced apart second and third conductive portions, the second conductive portion being over the dielectric portion and electrically isolated from the first conductive portion by the dielectric portion, and the third conductive portion is over, and electrically contacting, a second part of the first conductive portion; and
forming control lines for independently driving the first and second conductive portions.
4 Assignments
0 Petitions
Accused Products
Abstract
A select gate structure for a non-volatile storage system include a select gate and a coupling electrode which are independently drivable. The coupling electrode is adjacent to a word line in a NAND string and has a voltage applied which reduces gate induced drain lowering (GIDL) program disturb of an adjacent unselected non-volatile storage element. In particular, an elevated voltage can be applied to the coupling electrode when the adjacent word line is used for programming. A reduced voltage is applied when a non-adjacent word line is used for programming. The voltage can also be set based on other programming criterion. The select gate is provided by a first conductive region while the coupling electrode is provided by a second conductive region formed over, and isolated from, the first conductive region.
49 Citations
14 Claims
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1. A method for fabricating a select gate structure, comprising:
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forming a first conductive portion over a substrate; forming a dielectric portion over a first part of the first conductive portion and over the substrate; forming a conductive layer over the first conductive portion and the dielectric portion; etching the conductive layer to form spaced apart second and third conductive portions, the second conductive portion being over the dielectric portion and electrically isolated from the first conductive portion by the dielectric portion, and the third conductive portion is over, and electrically contacting, a second part of the first conductive portion; and forming control lines for independently driving the first and second conductive portions. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for fabricating a select gate structure, comprising:
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forming a first conductive portion over an insulating layer on a substrate; forming a second conductive portion over a first part of the first conductive portion, the second conductive portion being electrically coupled to the first conductive portion; forming a dielectric portion over a second part of the first conductive portion; forming a third conductive portion over the dielectric portion, the third conductive portion being electrically isolated from the first conductive portion by the dielectric portion and spaced apart from the second conductive portion, the second and third conductive portions are formed by forming a conductive layer over the first conductive portion and the dielectric portion and etching the conductive layer; and forming a protective dielectric layer which covers an exposed portion of the first conductive portion between the second and third conductive portions. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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Specification