Method for manufacturing an integrated circuit with fully depleted and partially depleted transistors

• US 7,691,727 B2
• Filed: 08/29/2007
• Issued: 04/06/2010
• Est. Priority Date: 08/31/2006
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Crolles 2 SAS (STMicroelectronics NV), STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Marty, Michel, Coronel, Philippe
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): Kusumakar; Karen M
• Application Number:
  US11/846,622
• Publication Number:
  US 20080064174A1
• Time in Patent Office: 951 Days
• Field of Search: 438/33, 438/68, 438/153, 438/154, 438/199, 438/275, 438/464
• US Class Current: 438/464
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

Claims

1. A method for manufacturing an integrated circuit containing fully depleted MOS transistors and partially depleted MOS transistors, comprising the steps of:

a) forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate to form a structure;

b) attaching an upper surface of the formed structure to a support wafer;

c) eliminating said substrate until the silicon-germanium layer is apparent;

d) depositing a mask and opening this mask at the locations of transistors which are desired to be fully depleted;

e) oxidizing the silicon-germanium at the locations of transistors which are desired to be fully depleted in conditions such that a condensation phenomenon occurs and that the front between the silicon and the silicon-germanium moves in the silicon layer; and

f) eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

2. The method of claim 1, wherein step a) comprises the step of coating the structure with an assembly of layers, the last one of which is a polished planar layer.

3. The method of claim 2, wherein said polished planar layer is a silicon oxide layer.

4. The method of claim 1, wherein step b) comprises the step of applying the structure on a silicon wafer by molecular bonding.

5. The method of claim 1, wherein said thin silicon layer has an initial thickness on the order of from 50 to 70 nm and a thickness after thinning on the order of from 10to 20 nm.

6. The method of claim 1, further comprising the step of forming contacts on the side from which the substrate has been eliminated to electrically couple to the transistors.

7. The method of claim 1, further comprising the step of placing a new wafer on the side from which the substrate has been eliminated.

8. A method for manufacturing an integrated circuit containing fully depleted MOS transistors and partially depleted MOS transistors, comprising the steps of:

a) forming similar MOS transistors on a silicon layer formed on a silicon-germanium layer to form a structure;

b) oxidizing the silicon-germanium at the locations of transistors which are desired to be fully depleted in conditions such that a condensation phenomenon occurs and that the front between the silicon layer and the silicon-germanium layer moves in the silicon layer; and

c) eliminating a resulting oxidized portion and a silicon-germanium portion from the locations of transistors which are desired to be fully depleted, whereby transistors, each with a thinned silicon layer, is formed.

9. The method of claim 8, further comprising coating the structure with an assembly of layers and polishing the last layer to produce a polished planar layer.

10. The method of claim 9, wherein coating the structure with an assembly of layers comprises providing a silicon oxide layer as the last layer.

11. The method of claim 9, further comprising molecular bonding the assembly of layers to a silicon wafer.

12. The method of claim 8, wherein oxidizing the silicon-germanium layer comprises oxidizing until a resulting thickness of the silicon layer is between approximately 10nm and 20nm.

13. The method of claim 8, further comprising forming contacts to electrically couple with the transistors.

14. The method of claim 9, further comprising placing a wafer over the assembly of layers.

15. The method of claim 9, wherein coating the structure with an assembly of layers comprises coating the structure with an assembly of layers alternately containing insulating layers and portions of conductive layers.