Method for manufacturing an integrated circuit with fully depleted and partially depleted transistors
First Claim
1. A method for manufacturing an integrated circuit containing fully depleted MOS transistors and partially depleted MOS transistors, comprising the steps of:
- a) forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate to form a structure;
b) attaching an upper surface of the formed structure to a support wafer;
c) eliminating said substrate until the silicon-germanium layer is apparent;
d) depositing a mask and opening this mask at the locations of transistors which are desired to be fully depleted;
e) oxidizing the silicon-germanium at the locations of transistors which are desired to be fully depleted in conditions such that a condensation phenomenon occurs and that the front between the silicon and the silicon-germanium moves in the silicon layer; and
f) eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.
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Accused Products
Abstract
A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.
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Citations
15 Claims
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1. A method for manufacturing an integrated circuit containing fully depleted MOS transistors and partially depleted MOS transistors, comprising the steps of:
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a) forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate to form a structure; b) attaching an upper surface of the formed structure to a support wafer; c) eliminating said substrate until the silicon-germanium layer is apparent; d) depositing a mask and opening this mask at the locations of transistors which are desired to be fully depleted; e) oxidizing the silicon-germanium at the locations of transistors which are desired to be fully depleted in conditions such that a condensation phenomenon occurs and that the front between the silicon and the silicon-germanium moves in the silicon layer; and f) eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for manufacturing an integrated circuit containing fully depleted MOS transistors and partially depleted MOS transistors, comprising the steps of:
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a) forming similar MOS transistors on a silicon layer formed on a silicon-germanium layer to form a structure; b) oxidizing the silicon-germanium at the locations of transistors which are desired to be fully depleted in conditions such that a condensation phenomenon occurs and that the front between the silicon layer and the silicon-germanium layer moves in the silicon layer; and c) eliminating a resulting oxidized portion and a silicon-germanium portion from the locations of transistors which are desired to be fully depleted, whereby transistors, each with a thinned silicon layer, is formed. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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Specification