Super GTO-based power blocks

• US 7,692,211 B1
• Filed: 10/02/2001
• Issued: 04/06/2010
• Est. Priority Date: 07/03/2001
• Status: Active Grant

• Current Assignee: Excelitas Technologies Corporation (Excelitas Technologies Holdings LLC)
• Original Assignee: Silicon Power Corporation
• Inventors: Pattanayak, Deva, Temple, Vic, Al-Marayati, Sabih, Holroyd, Forrest
• Primary Examiner(s): Nadav; Ori
• Application Number:
  US09/968,615
• Time in Patent Office: 3,108 Days
• Field of Search: 257/138, 257147-153, 257163-172
• US Class Current: 257/150
• CPC Class Codes: H01L 24/72 Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/744 Gate-turn-off devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01042 Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01075 Rhenium [Re]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19043 being a resistor
• CPC Class Codes: H01L 2924/30107 Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

A gate turn-off thyristor (GTO) device has a lower portion, an upper portion and a lid. The lower portion has a lower base region of a first conductivity type, and a lower emitter region of a second conductivity type disposed at or from a lower surface of the lower base region. A lower junction is formed between the lower base region and the lower emitter region. The upper portion has an upper base region of the second conductivity type, and upper emitter regions of the first conductivity type disposed at or from an upper surface of the upper base region. An upper-lower junction is formed between the lower base region and the upper base region, and upper junctions are formed between the upper base region and the upper emitter regions. The upper base region and upper emitter regions form an upper base surface with first conductive contacts to the upper base region alternating with second conductive contacts to the upper emitter regions. The lid has a layer of insulator with upper and lower surfaces. Upper metal stripes extend along the upper surface of the insulator, and lower metal stripes extend along the lower surface of the insulator. The upper and lower metal stripes are connected together by vias that extend through the insulator. One set of the lower metal stripes contacts the first conductive contacts, but not the second conductive contacts. Another set of the lower metal stripes contacts the second conductive contacts, but not the first conductive contacts.

Claims

1. A gate turn-off thyristor device comprising:

a lower portion having at least one lower base region of a first conductivity type and at least one lower emitter region of a second conductivity type;

an upper portion situated above said lower portion, said upper portion having a plurality of upper base regions of the second conductivity type and a plurality of upper emitter regions of the first conductivity type, wherein the plurality of upper base regions each forms one of a plurality of first conductive contacts and the plurality of upper emitter regions each forms one of a plurality of second conductive contact, the first conductive contacts alternating with the second conductive contacts and forming a top upper surface of the upper portion, wherein the top upper surface is a planar surface, wherein each of said plurality of first conductive contacts and each of said plurality of second conductive contacts are parallel to each other from a plan view;

an intermediate layer having first regions of a first metal alternating with second regions of a second metal and non-conductivity regions between the first regions and the second regions, the first regions of said intermediate layer directly connected to the first conductive contacts, and the second regions of said intermediate layer directly connected to the second conductive contacts;

a dielectric layer formed over said intermediate layer, the dielectric layer having openings; and

,

first and second metal stripes formed over said dielectric layer to traverse the first and second regions of said intermediate layer, said first metal stripes directly contacting the first regions of said intermediate layer through the openings in said dielectric layer and said second metal stripes directly contacting the second regions of said intermediate layer through the openings in said dielectric layer, wherein said lower portion and said upper portion form said gate turn-off thyristor device.

2. The device of claim 1, wherein the plurality of upper emitter regions each comprises at least one finger having a width of less than 100 microns.

3. The device of claim 1, wherein the upper surface of the plurality of upper base regions each comprises a finger having a width of less than 100 microns.

4. The device of claim 1, further comprising a lid having a layer of insulator with upper and lower surfaces, at least one upper metal stripe extending along the upper surface of the insulator, at least one lower metal stripe extending along the lower surface of the insulator, wherein a first one of the at least one lower metal stripe, and a second one of the at least one lower metal stripe is connected to at least two of the second conductive contacts, said lid further comprising conductive vias directly connecting the at least one upper metal stripe with the at least one lower metal stripe, wherein said first and second metal stripes further contact a respective one of the first and second ones of the at least one lower metal stripes of said lid.

5. The device of claim 4, wherein the said first and second ones of the lower metal stripes cross with said upper emitter regions.

6. The device of claim 4, wherein the upper and lower metal stripes are elongated, and the upper metal stripes cross with the lower metal stripes.

7. The device of claim 1, wherein the first and second conductive contacts have a combined total width of less than 0.5 cm.

8. The device of claim 4, wherein each lower metal stripe is connected to at least two of the first and second conductive contacts.

9. The device of claim 4, wherein at least one upper metal stripe connects to one or more electrodes on a control device mounted on said lid.

10. The device of claim 1, the lower portion comprising a substrate wafer, wherein the upper base region and upper emitter regions are diffused from an upper surface of the wafer to form planar junctions.

11. The device of claim 1, wherein said upper portion comprises a dense arrangement of upper emitter regions.

12. The device of claim 1, wherein the first and second conductive contacts alternate in a regular repeating form.

13. The device of claim 1, wherein said gate turn-off thyristor turns off a current density of at least 500 A/cm2.

14. The device of claim 1, wherein the plurality of upper emitter regions has a repeating pattern along a cell of good and moderate injection regions, and/or good and moderate contact impedance regions, and/or wider and narrower emitter regions.

15. The device of claim 4, wherein a control device is mounted on said lid, the control device controlling said gate turn-off thyristor device.

16. The device of claim 1, further comprising a controlled thyristor connected to the plurality of upper base regions and providing fast turn on of said gate turn-off thyristor device.

17. The device of claim 1, further comprising an integrated gate controlled transistor connected to the plurality of upper base regions.

18. The device of claim 1, wherein the differential induction between the upper base region and the upper emitter region is less than one percent of the total inductance of said gate turn-off thyristor device.

19. The device of claim 1, wherein the first conductive contacts and the second conductive contacts are coplanar and the plurality of upper base regions and plurality of upper emitter regions are arranged to form an even and continuous upper surface.

20. The device of claim 1, wherein the first conductive contacts and the second conductive contacts form a repeating pattern of at least one of the plurality of first conductive contacts alternating with at least one of the plurality of second conductive contacts.

21. The device of claim 1, wherein the upper portion further comprises at least one enhanced base region of a first conductivity type, the at least one enhanced base region positioned between the plurality of upper emitter regions and enhancing contact between the plurality of upper base regions and the plurality of upper emitter regions.

22. The device of claim 1, further comprising at least one lower junction formed between the at least one lower base region and the at least one lower emitter region, at least one upper junction formed between the plurality of upper base regions and the plurality of upper emitter regions, an upper-lower junction formed between said at least one lower base region and said plurality of upper base regions;

the lower junction, upper junction and upper-lower junctions forming a junction series through which forward current can flow in a latched-on condition, wherein the upper junction, upper surface of the upper portion, first and second conductive contacts and vias enhance current flow uniformity and minimize inductance.

23. The device of claim 1, wherein said first and second metal stripes are substantially perpendicular to said first and second regions.

24. A gate turn-off thyristor device comprising:

an upper portion having a plurality of upper base regions of a second conductivity type, and a plurality of upper emitter regions of a first conductivity type, wherein the a plurality of upper base regions each forms first conductive contacts and the plurality of upper emitter regions each forms second conductive contacts, the first conductive contacts alternating with the second conductive contacts and arranged to form a top upper surface of the upper portion, wherein the top upper surface is a planar surface, and wherein each of said plurality of first conductive contacts and each of said second conductive contacts are parallel to each other from a plan view;

an intermediate layer having first regions of a first metal alternating with second regions of a second metal and non-conductivity regions between the first regions and the second regions, the first regions of said intermediate layer directly connected to the first conductive contacts and the second regions of said intermediate layer directly connected to the second conductive contacts; and

,

a dielectric layer with a plurality of first openings and a plurality of second openings, a first metal stripe and a second metal stripe, said first metal stripe directly contacting the first regions through the plurality of first openings and said second metal stripe directly contacting the second regions through the plurality of second openings, wherein said first and second metal stripes are substantially perpendicular to said first and second regions, wherein said upper portion and a first conductivity type lower portion formed below the upper portion, form said gate thyristor device.

25. The device of claim 24, wherein the plurality of upper emitter regions each comprises at least one finger having a width of less than 100 microns.

26. The device of claim 24, wherein the upper surface of the plurality of upper base regions each comprises a finger having a width of less than 100 microns.

27. The device of claim 24, wherein the first and second conductive contacts have a combined total width of less than 0.5 cm.

28. The device of claim 24, wherein said upper portion comprises a dense arrangement of upper emitter regions.

29. The device of claim 24, wherein the first and second conductive contacts alternate in a regular repeating form.

30. The device of claim 24, wherein said gate turn-off thyristor turns off a current density of at least 500 A/cm2.

31. The device of claim 24, wherein the plurality of upper emitter regions has a repeating pattern along a cell of good and moderate injection regions, and/or good and moderate contact impedance regions, and/or wider and narrower emitter regions.

32. The device of claim 24, further comprising a controlled thyristor connected to the plurality of upper base regions and providing fast turn on of said gate turn-off thyristor device.

33. The device of claim 24, further comprising an integrated gate controlled transistor connected to the plurality of upper base regions.

34. The device of claim 24, wherein the differential induction between the upper base region and the upper emitter region is less than one percent of the total inductance of said gate turn-off thyristor device.

35. The device of claim 24, wherein the upper surface is level.

36. The device of claim 24, wherein the first conductive contacts and the second conductive contacts form a repeating pattern of at least one of the plurality of first conductive contacts alternating with at least one of the plurality of second conductive contacts.

37. The device of claim 24, wherein the upper portion further comprises at least one enhanced base region of a first conductivity type, the at least one enhanced base region positioned between the plurality of upper base regions and enhancing contact between the plurality of upper base regions and the plurality of upper emitter regions.

38. The device of claim 24, wherein said upper emitter regions have an area of reduced turn off capability.

39. The device of claim 24, further comprising a lid comprising a layer of insulator with upper and lower surfaces, upper metal stripes extending along the upper surface of the insulator, lower metal stripes extending along the lower surface of the insulator, wherein a first one of the lower metal stripes is connected with at least two of the first conductive contacts but not the second conductive contacts, and a second one of the lower metal stripes is connected with at least two of the second conductive contacts but not the first conductive contacts, said lid further comprising conductive vias connecting the upper metal stripes with the lower metal stripes.

40. The device of claim 39, wherein the said first and second ones of the lower metal stripes cross with said upper emitter regions.

41. The device of claim 39, wherein the upper and lower metal stripes are elongated, and the upper metal stripes cross with the lower metal stripes.

42. The device of claim 39, wherein each lower metal stripe contacts at least two of the first and second conductive contacts.

43. The device of claim 39, wherein at least one upper metal stripe connects to one or more electrodes on a control device mounted on said lid.

44. The device of claim 39, wherein a control device is mounted on said lid, the control device controlling said gate turn-off thyristor device.

45. The device of claim 39, wherein said device establishes a substantially uniform current path from the first or second upper metal stripes of said lid via said upper portion to the respective lower base region or lower emitter region of said lower portion.

46. A gate turn-off thyristor device comprising:

an upper layer having a base region and emitter regions, wherein the base region and the emitter regions form a top surface at which said emitter regions are on opposite sides of said base region, wherein the top surface of the base region and said emitter regions is a planar surface, wherein said base region and each of said emitter regions are parallel to each other from a plan view;

an intermediate layer having first conductive contacts alternating with second conductive contacts, wherein each of the first conductive contacts and said second conductive contacts comprise a narrow elongated stripe, each of said first conductive contacts is directly connected to said base region, and each of said second conductive contacts is directly connected to a respective one of said emitter regions;

a dielectric layer with a plurality of first openings and a plurality of second openings; and

,

a first metal stripe and a second metal stripe, said first metal stripe directly contacting the first conductive contacts through the first openings and said second metal stripe directly contacting the second conductive contacts through the second openings, wherein said first and second metal stripes are substantially wider than said first and second conductive contacts, wherein said upper layer and a first conductivity type lower layer formed below the upper layer form said gate turn-off thyristor device.

47. The device of claim 46, wherein said first and second metal stripes are substantially perpendicular to said first and second conductive contacts.

48. The device of claim 46, wherein each of said emitter regions of said upper layer have an area of reduced turn off capability.

49. The device of claim 46, further comprising a lid having a second insulator layer with first and second upper metal stripes extending along an upper surface of the insulator layer, first and second lower metal stripes extending along a lower surface of the insulator substantially perpendicular to the first and second upper metal stripes, and conductive vias connecting the first and second upper metal stripes with the first and second lower metal stripes, whereby the first and second lower metal stripes are in contact with and are substantially thicker than the first and second metal stripes of said dielectric layer.

50. The device of claim 49, wherein said device establishes a substantially uniform current path from the first or second upper metal stripes of said lid via said first insulator layer and said dielectric layer to the respective base region or emitter regions of said upper layer.

51. The device of claim 46, wherein the upper layer further comprises an enhanced base region, the enhanced base region enhancing contact between the base region and the plurality of emitter regions.