Nonvolatile semiconductor memory device
First Claim
1. A nonvolatile semiconductor memory device comprising:
- a semiconductor substrate in which a pair of impurity regions is formed with a channel formation region interposed therebetween; and
a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate,wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less, andwherein a band gap of the layer of the floating gate is smaller than a band gap of the channel formation region in the semiconductor substrate.
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Abstract
A nonvolatile semiconductor memory device which is superior in writing and charge holding properties, including a semiconductor substrate in which a channel formation region is formed between a pair of impurity regions formed with an interval, and a first insulating layer, a floating gate, a second insulating layer, and a control gate over an upper layer portion of the semiconductor substrate. It is preferable that a band gap of a semiconductor material forming the floating gate be smaller than that of the semiconductor substrate. For example, it is preferable that the band gap of the semiconductor material forming the floating gate be smaller than that of the channel formation region in the semiconductor substrate by 0.1 eV or more. This is because, by decreasing the bottom energy level of a conduction band of the floating gate electrode to be lower than that of the channel formation region in the semiconductor substrate, carrier injecting and charge holding properties are improved.
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Citations
32 Claims
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1. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate in which a pair of impurity regions is formed with a channel formation region interposed therebetween; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less, and wherein a band gap of the layer of the floating gate is smaller than a band gap of the channel formation region in the semiconductor substrate. - View Dependent Claims (2, 3)
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4. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate in which a pair of impurity regions is formed with a channel formation region interposed therebetween; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less, and wherein the floating gate has a higher electron affinity than silicon. - View Dependent Claims (5)
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6. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate in which a pair of impurity regions is formed with a channel formation region interposed therebetween; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less, and wherein a barrier energy with respect to electrons of the floating gate, formed from the first insulating layer is higher than a barrier energy with respect to electrons of the channel formation region in the semiconductor substrate, formed from the first insulating layer. - View Dependent Claims (7)
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8. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate having a first conductivity type and including a second conductivity type well, wherein a pair of first conductivity type impurity regions is formed with a channel formation region interposed therebetween in the second conductivity type well; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the floating gate is a layer comprising germanium or a germanium, compound with a thickness of 1 nm or more and 20 nm or less. - View Dependent Claims (9, 10)
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11. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate in which a pair of impurity regions is formed with a channel formation region interposed therebetween; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less, and wherein the floating gate is sandwiched between a first silicon nitride layer of the first insulating layer and a second silicon nitride layer of the second insulating layer. - View Dependent Claims (12, 13, 14)
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15. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate in which a pair of impurity regions is formed with a channel formation region interposed therebetween; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the first insulating layer comprises a first silicon oxide layer and a first silicon nitride layer which are sequentially stacked from an upper surface of the semiconductor substrate; wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less, and wherein a band gap of the layer of the floating gate is smaller than a band gap of the channel formation region in the semiconductor substrate. - View Dependent Claims (16, 17, 18)
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19. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate in which a pair of impurity regions is formed with a channel formation region interposed therebetween; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the first insulating layer comprises a first silicon oxide layer and a first silicon nitride layer which are sequentially stacked from an upper surface of the semiconductor substrate; wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less, and wherein the floating gate has a higher electron affinity than silicon. - View Dependent Claims (20, 21)
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22. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate in which a pair of impurity regions is formed with a channel formation region interposed therebetween; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the first insulating layer comprises a first silicon oxide layer and a first silicon nitride layer which are sequentially stacked from an upper surface of the semiconductor substrate; wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less, and wherein a barrier energy with respect to electrons of the floating gate, formed from the first silicon oxide layer is higher than a barrier energy with respect to electrons of the channel formation region in the semiconductor substrate, formed from the first silicon oxide layer. - View Dependent Claims (23, 24)
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25. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate having a first conductivity type and including a second conductivity type well, wherein a pair of first conductivity type impurity regions is formed with a channel formation region interposed therebetween in the second conductivity type well; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the first insulating layer comprises a first silicon oxide layer and a first silicon nitride layer which are sequentially stacked from an upper surface of the semiconductor substrate; and wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less. - View Dependent Claims (26, 27, 28)
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29. A nonvolatile semiconductor memory device comprising:
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a semiconductor substrate in which a pair of impurity regions is formed with a channel formation region interposed therebetween; and a first insulating layer, a floating gate, a second insulating layer, and a control gate which are overlapped with the channel formation region in the semiconductor substrate, wherein the first insulating layer comprises a first silicon oxide layer and a first silicon nitride layer which are sequentially stacked from an upper surface of the semiconductor substrate; wherein the floating gate is a layer comprising germanium or a germanium compound with a thickness of 1 nm or more and 20 nm or less, and wherein the floating gate is sandwiched between the first silicon nitride layer of the first insulating layer and a second silicon nitride layer of the second insulating layer. - View Dependent Claims (30, 31, 32)
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Specification