System and method for ESD protection

• US 7,692,247 B2
• Filed: 07/26/2007
• Issued: 04/06/2010
• Est. Priority Date: 11/12/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Lu, Fang, Woo, Agnes N., Kindsfater, Kenneth R.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US11/878,750
• Publication Number:
  US 20080036037A1
• Time in Patent Office: 985 Days
• Field of Search: 257/355, 257/356, 257/357, 257/360
• US Class Current: 257/355
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 7/10 : for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers
• CPC Class Codes: H04B 1/28 : the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

Claims

1. An electrostatic discharge (ESD) protection system for an integrated circuit die that includes a circuit core and a plurality of bond pads surrounding the circuit core, comprising:

a localized power supply bus disposed within the circuit core;

a localized ground bus disposed within the circuit core;

a ground ring disposed in an area between the plurality of bond pads and a periphery of the integrated circuit die; and

a ESD clamp coupled between the localized ground bus and the ground ring for providing a low impedance discharge path between the localized ground bus and the ground ring, wherein the ESD clamp is disposed between two adjacent bond pads.

2. The ESD protection system of claim 1, wherein the ESD clamp is non-overlapping with respect to the two adjacent bond pads.

3. The ESD protection system of claim 1, further comprising a second ESD clamp coupled between the localized power supply bus and the localized ground bus.

4. The ESD protection system of claim 3, wherein the second ESD clamp comprises a pair of anti-parallel diodes.

5. The ESD protection system of claim 3, further comprising a power supply ring disposed in an area between the plurality of bond pads and the periphery of the integrated circuit die.

6. The ESD protection system of claim 1, wherein a bond pad in the plurality of bond pads is coupled to the localized power supply bus.

7. The ESD protection system of claim 6, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

8. The ESD protection system of claim 1, wherein a bond pad in the plurality of bond pads is coupled to the localized ground bus.

9. The ESD protection system of claim 8, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

10. The ESD protection system of claim 1, wherein a bond pad in the plurality of bond pads is coupled to the ground ring.

11. The ESD protection system of claim 10, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

12. The ESD protection system of claim 1, wherein the ESD clamp comprises a pair of anti-parallel diodes.

13. The ESD protection system of claim 1, wherein the ground ring is coupled to a pin of an integrated circuit package.

14. The ESD protection system of claim 1, wherein the plurality of bond pads is staggered.

15. The ESD protection system of claim 1, further comprising a power supply ring disposed in an area between the plurality of bond pads and the periphery of the integrated circuit die;

and

a second ESD clamp coupled between the localized power supply bus and the power supply ring.

16. The ESD protection system of claim 15, wherein the second ESD clamp comprises a pair of anti-parallel diodes.

17. The ESD protection system of claim 15, wherein the power supply ring is coupled to a bond pad in the plurality of bond pads.

18. The ESD protection system of claim 17, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

19. The ESD protection system of claim 15, wherein the second ESD clamp is disposed between two adjacent bond pads.

20. The ESD protection system of claim 1, further comprising a second ESD clamp coupled between the localized power supply bus and the ground ring.

21. The ESD protection system of claim 20, wherein the second ESD clamp comprises a pair of anti-parallel diodes.

22. The ESD protection system of claim 20, wherein the second ESD clamp is disposed between two adjacent bond pads.

23. The ESD protection system of claim 1, further comprising a shunt transistor coupled between said ground ring and a bond pad.

24. The ESD protection system of claim 1, wherein said ground ring is at a non-zero potential.

25. An electrostatic discharge (ESD) protection system for an integrated circuit die that includes a circuit core and a plurality of bond pads surrounding the circuit core, comprising:

a localized power supply bus disposed within the circuit core;

a localized ground bus disposed within the circuit core;

a partial ground ring structure disposed in an area between the plurality of bond pads and a periphery of the integrated circuit die;

wherein the partial ground ring structure includes a first terminating point and a second terminating point, the first and second terminating points forming a gap for preventing an eddy current; and

an ESD clamp coupled between the localized ground bus and the partial ground ring structure for providing a low impedance discharge path between the localized ground bus and the partial ground ring structure, wherein the ESD clamp is disposed between two adjacent bond pads.

26. The ESD protection system of claim 25, wherein the ESD clamp is non-overlapping with respect to the two adjacent bond pads.

27. The ESD protection system of claim 25, further comprising a second ESD clamp coupled between the localized power supply bus and the localized ground bus.

28. The ESD protection system of claim 25, wherein the second ESD clamp comprises a pair of anti-parallel diodes.

29. The ESD protection system of claim 25, wherein a bond pad in the plurality of bond pads is coupled to the localized power supply bus.

30. The ESD protection system of claim 29, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

31. The ESD protection system of claim 25, wherein a bond pad in the plurality of bond pads is coupled to the localized ground bus.

32. The ESD protection system of claim 31, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

33. The ESD protection system of claim 25, wherein a bond pad in the plurality of bond pads is coupled to the partial ground ring structure.

34. The ESD protection system of claim 33, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

35. The ESD protection system of claim 25, wherein the ESD clamp comprises a pair of anti-parallel diodes.

36. The ESD protection system of claim 25, wherein the partial ground ring structure is coupled to a pin of an integrated circuit package.

37. The ESD protection system of claim 25, wherein the plurality of bond pads is staggered.

38. The ESD protection system of claim 25, further comprising a power supply ring disposed in an area between the plurality of bond pads and the periphery of the integrated circuit die;

and

a second ESD clamp coupled between the localized power supply bus and the power supply ring.

39. The ESD protection system of claim 38, further comprising a third ESD clamp coupled between the localized power supply bus and the localized ground bus.

40. The ESD protection system of claim 39, wherein the third ESD clamp comprises a pair of anti-parallel diodes.

41. The ESD protection system of claim 38, further comprising a third ESD clamp coupled between the localized power supply bus and the partial ground ring structure.

42. The ESD protection system of claim 41, wherein the third ESD clamp comprises a pair of anti-parallel diodes.

43. The ESD protection system of claim 41, wherein the third ESD clamp is disposed between two adjacent bond pads.

44. The ESD protection system of claim 38, wherein the second ESD clamp comprises a pair of anti-parallel diodes.

45. The ESD protection system of claim 38, wherein the power supply ring is coupled to a bond pad in the plurality of bond pads.

46. The ESD protection system of claim 45, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

47. The ESD protection system of claim 25, further comprising a shunt transistor coupled between said partial ground ring structure and a bond pad.

48. The ESD protection system of claim 25, wherein said partial ground ring structure is at a non-zero potential.

49. An electrostatic discharge (ESD) protection system for an integrated circuit die that includes a circuit core and a plurality of bond pads surrounding the circuit core, comprising:

a localized power supply bus disposed within the circuit core;

a localized ground bus disposed within the circuit core;

a ground ring disposed in an area between the plurality of bond pads and a periphery of the integrated circuit die;

a first ESD clamp coupled between the localized ground bus and the ground ring for providing a low impedance discharge path between the localized ground bus and the ground ring, wherein the first ESD clamp is disposed between two adjacent bond pads;

a partial power supply ring structure disposed in an area between the plurality of bond pads and the periphery of the integrated circuit die;

wherein the partial power supply ring structure includes a first terminating point and a second terminating point, the first and second terminating points forming a gap for preventing an eddy current; and

a second ESD clamp coupled between the localized power supply bus and the localized ground bus.

50. The ESD protection system of claim 49, wherein the first ESD clamp is non-overlapping with respect to the two adjacent bond pads.

51. The ESD protection system of claim 49, further comprising a third ESD clamp coupled between the localized power supply bus and the partial power supply ring structure.

52. The ESD protection system of claim 51, wherein the third ESD clamp is disposed between two adjacent bond pads.

53. The ESD protection system of claim 51, wherein the third ESD clamp comprises a pair of anti-parallel diodes.

54. The ESD protection system of claim 49, wherein a bond pad in the plurality of bond pads is coupled to the localized power supply bus.

55. The ESD protection system of claim 54, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

56. The ESD protection system of claim 49, wherein a bond pad in the plurality of bond pads is coupled to the localized ground bus.

57. The ESD protection system of claim 56, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

58. The ESD protection system of claim 49, wherein a bond pad in the plurality of bond pads is coupled to the ground ring.

59. The ESD protection system of claim 58, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

60. The ESD protection system of claim 49, wherein a bond pad in the plurality of bond pads is coupled to the partial power supply ring structure.

61. The ESD protection system of claim 60, wherein the bond pad is coupled to a circuit external to the periphery of the integrated circuit die.

62. The ESD protection system of claim 49, wherein the first ESD clamp comprises a pair of anti-parallel diodes.

63. The ESD protection system of claim 49, wherein the ground ring is coupled to a pin of an integrated circuit package.

64. The ESD protection system of claim 49, wherein the partial power supply ring structure is coupled to a pin of an integrated circuit package.

65. The ESD protection system of claim 49, wherein the plurality of bond pads is staggered.

66. The ESD protection system of claim 49, wherein the second ESD clamp comprises a pair of anti-parallel diodes.

67. The ESD protection system of claim 49, further comprising a third ESD clamp coupled between the partial power supply ring structure and the ground ring.

68. The ESD protection system of claim 67, wherein the third ESD clamp comprises a pair of anti-parallel diodes.

69. The ESD protection system of claim 67, wherein the third ESD clamp is disposed between two adjacent bond pads.

70. The ESD protection system of claim 49, further comprising a shunt transistor coupled between said ground ring and a bond pad.

71. The ESD protection system of claim 49, wherein said ground ring is at a non-zero potential.