Circuit board having a heating means and a hermetically sealed multi-chip package

• US 7,692,291 B2
• Filed: 04/12/2002
• Issued: 04/06/2010
• Est. Priority Date: 04/30/2001
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Kyu-Jin, Moon, Ho-Jeong
• Primary Examiner(s): Landau; Matthew C
• Assistant Examiner(s): Mitchell; James M
• Application Number:
  US10/121,515
• Publication Number:
  US 20020158330A1
• Time in Patent Office: 2,916 Days
• Field of Search: 257718-720, 257/706, 257/712, 257/675, 257/796, 257/722, 257/707, 257/723, 257/704, 257/705, 361/704, 361/705, 361/737
• US Class Current: 257/707
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01087 Francium [Fr]

Abstract

A circuit board having heating elements and a hermetically sealed multi-chip package. The multi-chip package includes a plurality of semiconductor chips, a substrate electrically coupled to the plurality of semiconductor chips, heat dissipation means, and a plurality of thermal interfaces disposed between the semiconductor chips and the heat dissipation means. The heat dissipation means forms a hermetically sealed cavity that encloses the semiconductor chips and at least a portion of the substrate. The circuit board includes a chip mounting surface, a chip mounting area on the chip mounting surface, the chip mounting area including a plurality of lands, and heating elements connected to the lands, the heating elements capable heating a joint formed between the lands and electrode pads of a semiconductor chip.

Claims

1. A multi-chip package comprising:

a substrate having a first surface, a second surface opposing the first surface, and side surfaces, the side surfaces are substantially perpendicular to the first and second surfaces;

a plurality of semiconductor chips electrically coupled to at least one of the first surface and the second surface of the substrate;

a heat dissipater thermally coupled to a portion of the first surface and a portion of the second surface of the substrate, the heat dissipater forming a hermetically sealed cavity around the semiconductor chips and at least a portion of the substrate, such that the heat dissipater is not mechanically coupled to an entire portion of said first and second surfaces, the heat dissipater being separated from one of the side surfaces by a distance; and

a plurality of thermal interfaces disposed between the semiconductor chips and the heat dissipater.

2. The multi-chip package of claim 1 wherein the substrate and the heat dissipation means only contact one another at a region where the hermetic seal is formed.

3. The multi-chip package of claim 1 wherein the hermetic seal forms a vacuum cavity around the semiconductor chips and at least a portion of the substrate.

4. The multi-chip package of claim 1 wherein the hermetically sealed cavity is filled with an inert gas.

5. The multi-chip package of claim 1 wherein the inert gas is selected from the group consisting of nitrogen, helium and neon.

6. The multi-chip package of claim 1 wherein each semiconductor chip is electrically connected to the substrate via a plurality of solder balls.

7. The multi-chip package of claim 1 wherein the substrate includes a plurality of land patterns and the land patterns include heating means.

8. The multi-chip package of claim 7 wherein the heating means is selected from the group consisting of nickel wire and chromium wire.

9. The multi-chip package of claim 7 wherein the land patterns are electrically coupled to a terminal section of the substrate and the terminal section of the substrate includes a power terminal for providing electrical energy to the heating means.

10. The multi-chip package of claim 1 wherein at least one of the semiconductor chips is mounted to the first surface of the substrate and at least another of the semiconductor chips is mounted to the second surface of the substrate.

11. The multi-chip package of claim 1 wherein at least one of the semiconductor chips is packaged in a CSP and at least another of the semiconductor chips is packaged in a WLP.

12. The multi-chip package of claim 1 wherein the heat dissipater comprises a first heat dissipation element and second heat dissipation element.

13. The multi-chip package of claim 1 wherein the substrate comprises:

a chip mounting surface;

at least one chip mounting area on the chip mounting surface, each chip mounting area including a plurality of lands; and

a plurality of individual spaced apart heating elements on each chip mounting area, the heating elements being capable heating joints formed between the lands and electrode pads of a semiconductor chip.

14. The multi-chip package of claim 13 wherein the substrate further comprises:

a power supply terminal connected to the heating elements.

15. The multi-chip package of claim 13 wherein the heating elements are formed by a nickel or chromium wires.

16. The multi-chip package of claim 13 wherein the heating elements are formed by a nickel or chromium wires having a spiral shape.

17. The multi-chip package of claim 13 wherein the heating elements heat the joints to a temperature that is higher than the melting point of the joints.

18. The multi-chip package of claim 13 wherein the lands are electrically connected to the electrode pads of the semiconductor chip via solder balls.

19. A multi-chip package, comprising:

a substrate having a first surface, a second surface, and side surfaces;

a plurality of semiconductor chips electrically coupled to at least one of the first surface and the second surface of the substrate;

a heat dissipater thermally coupled to a portion of the first surface and a portion of the second surface of the substrate, the heat dissipater forming a hermetically sealed cavity around the semiconductor chips and at least a portion of the substrate, such that the heat dissipater is not mechanically coupled to an entire portion of said first and second surfaces, the heat dissipater surrounds one of the side surfaces to form a distance between the side surface and the heat dissipater; and

a plurality of thermal interfaces disposed between the semiconductor chips and the heat dissipater.