Structure for modeling stress-induced degradation of conductive interconnects

• US 7,692,439 B2
• Filed: 05/22/2008
• Issued: 04/06/2010
• Est. Priority Date: 11/04/2005
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Clevenger, Lawrence A., Nguyen, Du B., Yang, Chih-Chao, Sullivan, Timothy D., Lee, Tom C., Gill, Jason P., McLaughlin, Paul S., Filippi, Ronald G., Li, Baozhen, Chanda, Kaushik, Agarwala, Birendra, Rathore, Hazara S., Cowley, Andrew P.
• Primary Examiner(s): Karlsen; Ernest F
• Application Number:
  US12/154,304
• Publication Number:
  US 20080231312A1
• Time in Patent Office: 684 Days
• Field of Search: 324/158.1, 324/537, 324/719, 324/763, 324/765, 257/48, 257/758, 257/767, 374/57
• US Class Current: 324/750.01
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

Claims

1. A structure representative of a conductive interconnect in a microelectronic element for purposes of modeling stress-induced degradation, comprising:

a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between said upper surface and said lower surface, said upper surface defining a horizontally extending plane, said metallic plate having a width in a widthwise direction, a length in a lengthwise direction transverse to said width, and a thickness in a vertical direction extending between said upper surface and said lower surface;

a lower via consisting essentially of at least one of conductive or semiconductive material having a top end in conductive communication with said metallic plate and a bottom end vertically displaced from said top end;

a lower element consisting essentially of at least one of conductive or semiconductive material in contact with said bottom end of said lower via;

an upper metallic via in at least substantial vertical alignment with said lower conductive via such that a line extending in said vertical direction through said metallic plate intersects said upper metallic via and said lower conductive via, said upper metallic via having a bottom end in conductive communication with said metallic plate and a top end vertically displaced from said bottom end, said upper metallic via having a width at least about ten times smaller than a larger one of said length of said metallic plate and said width of said metallic plate; and

an upper metallic line element in contact with said top end of said upper metallic via.

2. The structure as claimed in claim 1, wherein said bottom end of said upper metallic via contacts said metallic plate.

3. The structure as claimed in claim 1, wherein said lower via includes a semiconductor material.

4. The structure as claimed in claim 1, wherein said metallic plate has a plurality of dielectric filled openings extending vertically between said upper surface and said lower surface.

5. The structure as claimed in claim 4, wherein said plurality of dielectric filled openings are arranged as a plurality of parallel elongated openings in said lengthwise direction such that said metallic plate has a plurality of parallel elongated branches extending in said lengthwise direction.

6. The structure as claimed in claim 1, wherein the width of the upper metallic via is at least ten times smaller than the larger one of said length of said metallic plate and said width of said metallic plate.