Sense amplifier based flip-flop
First Claim
Patent Images
1. A circuit comprising:
- an input stage that is operative to receive a clock signal and a first and second input signal;
an output stage that is operative to receive the clock signal and to generate a first and second output signal based on the clock signal and the first and second input signals; and
a delay stage that is operatively coupled to the input and output stages and that comprises a first and second branch, wherein the second branch includes at least one more delay element than the first branch.
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Abstract
A circuit includes an input stage, an output stage, and a delay stage. The input stage is operative to receive a clock signal and a first and second input signal. The output stage is operative to receive the clock signal. The output stage is also operative to generate a first and second output signal based on the clock signal and the first and second input signals. The delay stage is operatively coupled to the input and output stages. The delay stage includes a first and second branch. The second branch includes at least one more delay element than the first branch.
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Citations
33 Claims
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1. A circuit comprising:
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an input stage that is operative to receive a clock signal and a first and second input signal; an output stage that is operative to receive the clock signal and to generate a first and second output signal based on the clock signal and the first and second input signals; and a delay stage that is operatively coupled to the input and output stages and that comprises a first and second branch, wherein the second branch includes at least one more delay element than the first branch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An Integrated circuit comprising:
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a latch state that is operative to generate an output in response to a first and second input, wherein the output is generated in response to the first input after a first delay and the output is generated in response to the second input after a second delay that is greater than the first delay; and a sense amplifier stage that is operative to generate the first and second inputs in response to a clock signal, wherein the first input is generated after the second delay and the second input is generated after the first delay, wherein the sense amplifier stage comprises a delay stage that comprises a first branch that is operative to provide the first delay and a second branch that is operative to provide the second delay and wherein the second branch includes at least one more delay element than the first branch. - View Dependent Claims (13, 14)
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15. A flip-flop comprising:
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an output stage that comprises; a first transistor having a first terminal operatively coupled to a voltage source, a second terminal, and a third terminal that is operative to receive a clock signal, a second transistor having fourth terminal operatively coupled to the first terminal, a fifth terminal operatively coupled to the second terminal, and a sixth terminal; a third transistor having a seventh terminal operatively coupled to the fourth terminal, an eighth terminal operatively coupled to the sixth terminal, and a ninth terminal operatively coupled to the fifth terminal; and a fourth transistor having a tenth terminal operatively coupled to the seventh terminal, an eleventh terminal operatively coupled to the eighth terminal, and a twelfth terminal that is operative to receive the clock signal; a delay stage that comprises a first and second branch, wherein the second branch includes at least one more delay element than the first branch, wherein the first branch comprises; a fifth transistor having a thirteenth terminal operatively coupled to the fifth terminal, a fourteenth terminal operatively coupled to an input stage, and a fifteenth terminal operatively coupled to the sixth terminal, and wherein the second branch comprises; a sixth terminal having an sixteenth terminal, a seventeenth terminal operatively coupled to the input stage, and an eighteenth terminal operatively coupled to the ninth terminal, and a seventh transistor having a nineteenth terminal operatively coupled to the eighth terminal, a twentieth terminal operatively coupled to the sixteenth terminal, and a twenty-first terminal operatively couple to the voltage source; and a latch stage operatively coupled to the second and eleventh terminals. - View Dependent Claims (16, 17, 18)
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19. A device comprising an integrated circuit that comprises:
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a latch stage that is operative to generate an output in response to a first and second input, wherein the output is generated in response to the first input after a first delay and the output is generated in response to the second input after a second delay that is greater than the first delay; a sense amplifier stage that is operative to generate the first and second inputs in response to a clock signal, wherein the first input is generated after the second delay and the second input is generated after the first delay, wherein the sense amplifier stage comprises a stage that comprises a first branch that is operative to provide the first delay and a second branch that is operative to provide the second delay and wherein the second branch includes at least one more delay element than the first branch. - View Dependent Claims (20, 21, 22)
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23. An integrated circuit design system comprising:
- a processor; and
memory operatively coupled to the processor that comprises a circuit design cell, comprising;a latch stage that is operative to generate an output in response to a first and second input, wherein the output is generated in response to the first input after a first delay and the output is generated in response to the second input after a second delay that is greater than the first delay; and a sense amplifier stage that is operative to generate the first and second inputs in response to a clock signal, wherein the first input is generated after the second delay and the second input is generated after the first delay, wherein the sense amplifier stage comprises a delay stage that comprises a first branch that is operative to provide the first delay and a second branch that is operative to provide the second delay and wherein the second branch includes at least one more delay element than the first branch.
- a processor; and
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24. A computer readable media storing instructions, said instructions adapted to provide a cell library, said cell library comprising data representing:
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an input stage that is operative to receive a clock signal and a first and second input signal; an output stage that is operative to receive the clock signal and to generate a first and second output signal based on the clock signal and the first and second input signals; and a delay stage that is operatively coupled to the input and output stages and that comprises a first and second branch, wherein the second branch includes at least one more delay element than the first branch. - View Dependent Claims (25, 26, 27)
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28. A computer readable media storing instructions, that when executed, provide a circuit design program that uses a cell library that comprises a data representing:
- a latch stage that is operative to generate an output in response to a first and second input, wherein the output is generated in response to the first input after a first delay and the output is generated in response to the second input after a second delay that is greater than the first delay; and
a sense amplifier stage that is operative to generate the first and second inputs in response to a clock signal, wherein the first input is generated after the second delay and the second input is generated after the first delay, wherein the sense amplifier stage comprises a delay stage that comprises a first branch that is operative to provide the first delay and a second branch that is operative to provide the second delay and wherein the second branch includes at least one more delay element than the first branch. - View Dependent Claims (29, 30, 31, 32)
- a latch stage that is operative to generate an output in response to a first and second input, wherein the output is generated in response to the first input after a first delay and the output is generated in response to the second input after a second delay that is greater than the first delay; and
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33. A circuit, comprising:
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a sense amplifier stage that comprises; an input stage that is operative to receive a clock signal and a first and second input signal; an output stage that is operative to receive the clock signal and to generate a first and second output signal based on the clock signal and the first and second input signals, wherein the first output signal is generated in response to the first input signal after a first delay and the second input signal is generated in response to the second input signal after a second delay that is greater than the first delay; and a delay stage, operatively coupled to the input and output stages, that comprises a first branch that is operative to provide the first delay and second branch that is operative to provide the second delay, wherein the second branch includes at least one more delay element than the first branch; and a latch stage, operatively coupled to the output stage, that is operative to generate a third output in response to the first output after the second delay and to generate the third output in response to the second output after a second delay that is greater than the first delay.
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Specification