Thin film transistor array panel and display device including the same

• US 7,692,617 B2
• Filed: 04/20/2005
• Issued: 04/06/2010
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Haeng-Won, Moon, Seung-Hwan, Kim, Dong-Gyu, Kang, Nam-Soo, Lee, Yong-Soon
• Primary Examiner(s): Dharia; Prabodh M
• Application Number:
  US11/111,093
• Publication Number:
  US 20060022201A1
• Time in Patent Office: 1,812 Days
• Field of Search: 345/87, 345/204, 345/88, 345/212, 345/173, 345/55, 345/206, 345 94-102, 257/72, 257/208, 257/693, 257/350, 257/40, 257/59, 349/73, 349/106, 349/187, 349/190, 349/153, 349/40, 349/189, 349/70, 349/71, 349/139, 349/43, 349/155, 349/122, 349/141, 438/689, 438/151, 313/504, 315/169.1, 348/333.09
• US Class Current: 345/98
• CPC Class Codes: G02F 1/1339 Gaskets; Spacers; Sealing of cells
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

Gate-driving circuitry of a thin film transistor array panel is formed on the same plane as a display area of the transistor array panel. The gate-driving circuitry includes driving circuitry and signal lines having apertures. Thus, a sufficient amount of light, even though illuminated from the thin film transistor array panel side, can reach a photosetting sealant overlapping at least in part the gate-driving circuitry. The thin film transistor array panel and the counter panel are put together air-tight and moisture-tight. Consequently, the gate-driving circuitry can avoid corrosion by moisture introduced from outside. Gate-driving circuitry malfunctions can also be reduced.

Claims

1. A thin film transistor array panel, the thin film transistor array panel having a gate line, a data line, a pixel electrode, a thin film transistor and a gate driving circuit formed on a substrate, wherein the gate driving circuit is formed simultaneously with the thin film transistor and comprises:

a driving circuitry outputting a gate signal to the gate line;

a first signal line electrically connected to the gate driving circuit, wherein an aperture of a predetermined width is formed in the first signal line.

2. The thin film transistor array panel of claim 1, wherein a width of a segment of the first signal line is smaller than or equal to 100 μ

m.

3. The thin film transistor array panel of claim 2, wherein the segment is a part of a boundary enclosing the aperture, and the width of the segment is between 20 μ

m and 30 μ

m.

4. The thin film transistor array panel of claim 1, wherein the first signal line is formed of a same layer as the gate line or the data line.

5. The thin film transistor array panel of claim 1, wherein the first signal line comprises at least two conductive material layers.

6. The thin film transistor array panel of claim 5, wherein one of the conductive material layers includes aluminum, aluminum alloy, silver, silver alloy, chrome, molybdenum, or molybdenum alloy.

7. The thin film transistor array panel of claim 1, wherein the gate-driving circuit further comprises second and third signal lines, and the driving circuitry includes a shift register having a plurality of cascaded stages generating an output signal.

8. The thin film transistor array panel of claim 7, wherein the first, second and third signal lines transmit a gate-off signal, a first clock signal and a second clock signal, respectively, to the shift register, the second clock signal having a phase different from the first clock.

9. The thin film transistor array panel of claim 7, wherein each of the first, second and third signal lines has an aperture.

10. The thin film transistor array panel of claim 7, wherein the gate driving circuit further comprises a fourth signal line transmitting an initialization signal to the shift register.

11. The thin film transistor array panel of claim 10, wherein the gate driving portion further comprises a bridge line electrically connecting one of the first, second, third and fourth lines to the shift register.

12. The thin film transistor array panel of claim 11, wherein the bridge line is formed of a different layer from the one of the first, second, third and fourth signal lines.

13. The thin film transistor array panel of claim 12, wherein the bridge line is electrically connected to the one of the first, second, third and fourth signal lines through a connection assistant.

14. The thin film transistor array panel of claim 12, wherein the connection assistant is transparent and connected to the bridge line and the one of the first, second, third and fourth signal lines through first and second contact holes, respectively.

15. The thin film transistor array panel of claim 1, wherein the driving circuitry includes a plurality of transistors connected in parallel and adjusted to form an aperture of a predetermined width among the transistors.

16. The thin film transistor array panel of claim 15, wherein the aperture has a width that is less than or equal to 100 μ

m.

17. A thin film transistor array panel comprising:

an insulating substrate;

a plurality of gate lines and a plurality of data lines formed on the insulating substrate;

a plurality of pixel electrodes formed on each pixel region defined by the plurality of gate lines and the plurality of data lines;

a plurality of thin film transistors electrically connected to one of the plurality of gate lines, one of the plurality of data lines and one of the plurality of pixel electrodes; and

a gate-driving circuit formed simultaneously with the thin film transistor on the insulating substrate, the gate-driving circuit including a plurality of signal lines transmitting external signals and a driving circuitry outputting gate signals to each of the plurality of gate lines in response to the external signals, wherein the plurality of signal lines includes a ladder or net shaped signal line.

18. The thin film transistor array panel of claim 17, wherein the ladder or net-shaped signal line includes a plurality of first branches and a plurality of second branches between and connecting the two adjacent first branches, the first and second branches enclosing an aperture.

19. The thin film transistor array panel of claim 17, wherein one of the first branches has a width that is between 20 μ

m and 30 μ

m.

20. The thin film transistor array panel of claim 17, the aperture has a width between 20 μ

m and 30 μ

m.

21. A thin film transistor array panel, comprising:

an insulating substrate;

a plurality of gate lines and a plurality of data lines formed on the insulating substrate;

a plurality of pixel electrodes, each pixel formed on each pixel region defined by the plurality of gate lines and the plurality of data lines;

a plurality of switching elements, each switching element electrically connected to one of the plurality of gate lines, one of the plurality of data lines and one of the plurality of pixel electrodes; and

a gate driving circuit formed simultaneously with the thin film transistor on the insulating substrate, the gate driving circuit including a plurality of signal lines transmitting gate driving signals and a driving circuitry outputting gate signals to each of the plurality of gate lines in response to the gate-driving signals, wherein the driving circuitry includes a plurality of transistors connected in parallel and adjusted to form an aperture among the transistors.

22. The thin film transistor array panel of claim 21, wherein the aperture has a width that is less than or equal to 100 μ

m.

23. A display device comprising:

a display panel having a first substrate with a plurality of gate lines, a gate-driving circuit and a plurality of data lines formed thereon, wherein the gate-driving circuit is formed simultaneously with the thin film transistor, a second substrate, a sealant disposed between the two substrates and a liquid crystal layer disposed into a space enclosed by the two substrates and the sealant, and

a data driving circuit outputting data signals to the plurality of data lines, wherein the gate-driving circuit includes a plurality of signal lines transmitting gate-driving signals and a driving circuitry outputting gate signals to the plurality of gate lines in response to the gate-driving signals, and wherein an aperture is formed on at least one signal line of the plurality of signal line.

24. The display device of claim 23, wherein the sealant includes a photosetting material, and the sealant overlaps the aperture at least in part.

25. The display device of claim 24, wherein an opaque region is formed on the second substrate, and the opaque region overlaps the sealant at least in part.

26. A method of providing a display device, the method comprising:

forming a plurality of gate lines, a plurality of data lines, a first plurality of thin film transistors, and a gate driving circuit on a first substrate, wherein the gate driving circuit is formed simultaneously with the thin film transistor and includes a signal line with an aperture and a driving circuitry that comprises a second plurality of thin film transistors;

forming an opaque region on a second substrate;

providing a liquid crystal layer disposed on one of the first and second substrates;

providing a sealant disposed one of the first and second substrates;

providing the first and second substrates aligned to each other; and

providing the sealant exposed to a light through the aperture.

27. The method of providing a display device of claim 26, wherein the aperture has a width between 20 μ

m and 30 μ

m.