Semiconductor memory device

• US 7,692,950 B2
• Filed: 01/07/2008
• Issued: 04/06/2010
• Est. Priority Date: 01/08/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Rhie, Hyoung-Seub
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/969,972
• Publication Number:
  US 20080165567A1
• Time in Patent Office: 820 Days
• Field of Search: 365/148, 365/63, 365/158
• US Class Current: 365/148
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H01L 27/101 including resistors or capacitors only

Abstract

There is provided a semiconductor memory device including; first and second active areas formed to extend in a first direction on a semiconductor substrate, first and second split word lines formed in a second direction on the semiconductor substrate, a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas, a first variable resistance element formed on the first active area between the first and second split word lines, a second variable resistance element formed on the second active area between the first and second split word lines, first and second bit lines extending in the first direction and respectively coupled to the first and second variable resistance elements.

Claims

1. A semiconductor memory device comprising:

first and second active areas extending in a first direction on a semiconductor substrate;

first and second split word lines extending in a second direction on the semiconductor substrate;

a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas;

a first variable resistance element formed on the first active area between the first and second split word lines;

a second variable resistance element formed on the second active area between the first and second split word lines;

first and second bit lines extending in the first direction, and respectively coupled to the first and second variable resistance elements,

a first contact coupling the first active area to the first variable resistance element;

a second contact formed on the opposite side of the first contact with respect to the first split word line and coupling the first active area to the common source line;

a third contact formed on the opposite side of the second contact with respect to the second split word line and coupling the first active area to the common source line;

a fourth contact coupling the second active area to the second variable resistance element;

a fifth contact formed on the opposite side of the fourth contact relative with respect to the first split word line and coupling the second active area to the common source line; and

a sixth contact formed on the opposite side of the fourth contact with respect to the second split word line and coupling the second active area to the common source line.

2. The semiconductor memory device of claim 1, wherein the first, second and third contacts are aligned as a first group in the first direction, and the fourth, fifth and sixth contacts are aligned as a second group in the first direction.

3. The semiconductor memory device of claim 2, wherein:

the common source line has a fishbone antenna-like shape and includes an axis source line extending in the first direction and a plurality of spine source lines protruding from the axis source line;

wherein the spine source lines are respectively coupled to the second, third, fifth, and sixth contacts.

4. The semiconductor memory device of claim 1, wherein the first and second variable resistance elements are formed on the common source line.

5. The semiconductor memory device of claim 1, wherein the first and second bit lines are formed on the common source line.

6. The semiconductor memory device of claim 1, wherein any one of at least two different data values is written in each of the first and second variable resistance elements in accordance with a potential difference between the common source line and either the first bit line or the second bit line corresponding to the variable resistance elements.

7. The semiconductor memory device of claim 6, further comprising:

a writing circuit selecting between the first variable resistance element or the second variable resistance element in response to a selection signal and writing the data in the selected variable resistance element.

8. The semiconductor memory device of claim 7, wherein the writing circuit comprises a selecting unit selecting the first bit line or the second bit line in response to the selection signal.

9. A semiconductor memory device comprising:

first and second split word lines formed on a semiconductor substrate;

a common source line having a fishbone antenna-like shape and including an axis source line intersecting the first and second split word lines and a plurality of spine source lines protruding from the axis source line; and

first and second bit lines intersecting the first and second split word lines.

10. The semiconductor memory device of claim 9, further comprising:

first and second variable resistance elements formed between the first and second split word lines, such that the first variable resistance element is disposed on an opposite side of the second variable resistance element with respect to the axis source line.

11. The semiconductor memory device of claim 10, wherein:

first and second spine source lines from the plurality of spine source lines formed on the opposite side of the first and second variable resistance elements with respect to the first split word line and protruding from the axis source line in opposite directions; and

third and forth spine source lines formed on the opposite side of the first and second variable resistance elements with respect to the second split word line and protruding from the axis source line in opposite direction.

12. The semiconductor memory device of claim 11, further comprising:

first and second active areas extending to intersect the first and second split word lines;

a first contact coupling the first active area to the first variable resistance element;

a second contact coupling the first active area to the first spine source line;

a third contact coupling the first active area to the third spine source line;

a fourth contact coupling the second active area to the second variable resistance element;

a fifth contact coupling the second active area to the second spine source line; and

a sixth contact coupling the second active area to the fourth spine source line.

13. The semiconductor memory device of claim 12, wherein the first, second and third contacts are aligned as a first group in the direction in which the first active area extends, and the fourth, fifth and sixth contacts are aligned as a second group in the direction in which the second active area extends.

14. The semiconductor memory device of claim 10, wherein the first and second variable resistance elements are formed on the common source line.

15. The semiconductor memory device of claim 9, wherein the first and second bit lines are formed on the common source line.

16. The semiconductor memory device of claim 10, wherein each of the first and second variable resistance elements contains nickel-oxide (NiO).

17. The semiconductor memory device of claim 10, wherein any one of at least two different data values is written in each of the first and second variable resistance elements in accordance with a potential difference between the common source line and either the first bit line or the second bit line corresponding to the variable resistance elements.

18. A semiconductor memory device comprising:

first and second active areas extending in a first direction on a semiconductor substrate;

first and second split word lines extending in a second direction on the semiconductor substrate;

a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas;

a first variable resistance element formed on the first active area between the first and second split word lines;

a second variable resistance element formed on the second active area between the first and second split word lines; and

first and second bit lines extending in the first direction, and respectively coupled to the first and second variable resistance elements,

wherein each of the first and second variable resistance elements contains nickel-oxide (NiO).