Apparatus and method for integrating nonvolatile memory capability within SRAM devices
First Claim
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1. A nonvolatile static random access memory (SRAM) device, comprising:
- a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data;
a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell;
wherein the magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device; and
a common programming node coupled to the pair of magnetic spin transfer devices, the common programming node configured implement programming of the magnetic spin transfer devices for storage cell data retention, and initialization of the storage cell with the retained data in the magnetic spin transfer devices.
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Abstract
A nonvolatile static random access memory (SRAM) device includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data and a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell. The magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device.
39 Citations
29 Claims
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1. A nonvolatile static random access memory (SRAM) device, comprising:
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a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured as a storage cell for a bit of data; a pair of magnetic spin transfer devices coupled to opposing sides of the storage cell; wherein the magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device; and a common programming node coupled to the pair of magnetic spin transfer devices, the common programming node configured implement programming of the magnetic spin transfer devices for storage cell data retention, and initialization of the storage cell with the retained data in the magnetic spin transfer devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of integrating nonvolatile capability within a static random access memory (SRAM) device, the method comprising:
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coupling a pair of magnetic spin transfer devices to opposing sides of an SRAM storage cell; the SRAM storage cell further comprising a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters configured to store a bit of data therein; wherein the magnetic spin transfer devices are configured to retain the storage cell data therein following removal of power to the SRAM device, and are further configured to initialize the storage cell with the retained data upon application of power to the SRAM device; and coupling a common programming node to the pair magnetic spin transfer devices, the common programming node configured to implement programming of the magnetic spin transfer devices for storage cell data retention, and initialization of the storage cell with the retained data in the magnetic spin transfer devices. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for implementing nonvolatile retention of a data bit stored man SRAM cell, the method comprising:
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charging a programming node to a first bias voltage about halfway between a logic high voltage and a logic low voltage of the SRAM cell; respectively coupling one side of a pair of magnetic spin transfer devices to opposing sides of an SRAM storage cell through activation of a pair of pass gate devices, with an opposite side of the pair of magnetic spin transfer devices coupled to the programming node, so as to pass current through a first of the magnetic spin transfer devices in a first direction, and to pass through a second of the magnetic spin transfer devices in a second, opposite direction; wherein passing current in the first direction causes programming of the first magnetic spin transfer device to a low resistance state, and passing current in the second direction causes programming of the second spin transfer device to a high resistance state; and removing a source of power to the SRAM cell upon achieving the low resistance state in the first magnetic spin transfer device, and achieving the high resistance state in the second magnetic spin transfer device; wherein the data stored in the SRAM cell prior to power source removal is maintained within the pair of magnetic spin transfer devices following power source removal. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29)
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Specification