Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection

• US 7,692,961 B2
• Filed: 08/02/2006
• Issued: 04/06/2010
• Est. Priority Date: 02/21/2006
• Status: Expired due to Fees

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Eitan, Boaz, Shainsky, Natalie
• Primary Examiner(s): Tran, Andrew Q
• Application Number:
  US11/462,011
• Publication Number:
  US 20070196982A1
• Time in Patent Office: 1,343 Days
• Field of Search: 365/185.03, 365/185.02, 365/185.16, 365/185.22, 365/185.24, 365/185.18, 365/185.28
• US Class Current: 365/185.02
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

Programming a NVM memory cell such as an NROM cell by using hot hole injection (HHI), followed by channel hot electron (CHE) injection. CHE injection increases the threshold voltage (Vt) of bits of memory cells that were disturbed (unnecessarily programmed) in HHI programming step. Page Write may be performed using a combination of only HHI, followed by CHE without any Erase.

Claims

1. A method for programming a plurality of memory cells, each cell having a program verify voltage (PV) and an erase verify voltage (EV), the method comprising:

programming first selected ones of the cells by decreasing the threshold voltage of the first selected ones of the cells to less than the program verify voltage (Vt<

PV); and

refreshing second selected ones of the cells by increasing the threshold voltage (Vt) of the second selected ones the cells to greater than the erase verify voltage (Vt>

EV).

2. The method of claim 1, wherein:

programming of said first selected ones of the cells is performed using Hot Hole Injection (HHI); and

the refreshing is performed using Channel Hot Electron (CHE) injection.

3. A device comprising:

a plurality of memory cells, each cell having a program verify voltage (PV) and an erase verify voltage (EV); and

a controller coupled to the plurality of memory cells for programming first selected ones of said cells by decreasing the threshold verify voltage of the first selected ones of the cells to less than the program verify voltage (Vt<

PV), and refreshing second selected ones of the cells by increasing the threshold voltage (Vt) of the second selected ones of the cells to greater than the erase verify voltage (Vt>

EV).

4. The device of claim 3, wherein programming of said first selected ones of the cells is performed using Hot Hole Injection (HHI), and the refreshing is performed using Channel Hot Electron (CHE) injection.

5. A circuit for operating a nonvolatile memory array comprising:

one or more charge pumps functionally associated with a plurality of memory cells, each cell having a program verify voltage (PV) and an erase verify voltage (EV); and

a controller coupled to the plurality of memory cells for programming first selected ones of said cells by decreasing the threshold voltage of the first selected ones of the cells to less than the program verify voltage (Vt<

PV), and refreshing second selected ones of the cells by increasing the threshold voltage (Vt) of the second selected ones of the cells to greater than the erase verify voltage (Vt>

EV).

6. The circuit of claim 5, wherein programming of said first selected ones of the cells is performed using Hot Hole Injection (HHI), and the refreshing is performed using Channel Hot Electron (CHE) injection.