Split gate memory cell for programmable circuit device

• US 7,692,972 B1
• Filed: 07/22/2008
• Issued: 04/06/2010
• Est. Priority Date: 07/22/2008
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp.
• Original Assignee: Actel Corporation (Microchip Technology Incorporated)
• Inventors: McCollum, John, Dhaoui, Fethi, Sadd, Michael, Wang, George
• Primary Examiner(s): Le, Thong Q
• Application Number:
  US12/177,680
• Time in Patent Office: 623 Days
• Field of Search: 365/185.26, 365/189.11, 365/185.01, 365/104
• US Class Current: 365/185.26
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data

Abstract

A split-gate memory cell, includes an n-channel split-gate non-volatile memory transistor having a source, a drain, a select gate over a thin oxide, and a control gate over a non-volatile gate material and separated from the select gate by a gap. A p-channel pull-up transistor has a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate. A switch transistor has first and second source/drain diffusions, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor. An inverter has an input coupled to the second source/drain diffusion of the switch transistor, and an output. A p-channel level-restoring transistor has a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverter.

Claims

1. A split-gate memory cell, including:

an n-channel split-gate non-volatile memory transistor having a source and a drain, the source and drain defining a channel, a select gate over a portion of the channel nearest the drain, and a control gate over a non-volatile charge retention structure over a portion of the channel nearest the source, the select gate and the control gate separated by a gap;

a p-channel pull-up transistor having a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, and a gate;

a switch transistor having a first source/drain diffusion, a second source/drain diffusion, and a gate coupled to the drains of the split-gate non-volatile memory transistor and the p-channel pull-up transistor;

an inverting buffer having an input coupled to the second source/drain diffusion of the switch transistor, and an output;

a p-channel level-restoring transistor having a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverting buffer.

2. The split-gate memory cell of claim 1 wherein the non-volatile charge retention structure is a floating gate.

3. The split-gate memory cell of claim 1 wherein the non-volatile charge retention structure is a region of isolated nanocrystals.

4. The split-gate memory cell of claim 1 wherein the non-volatile charge retention structure is a SONOS structure.

5. A split-gate memory cell, including:

an n-channel split-gate non-volatile memory transistor having a source and a drain, the source and drain defining a channel, a select gate over a portion of the channel nearest the drain, and a control gate over a non-volatile charge retention structure over a portion of the channel nearest the source, the select gate and the control gate separated by a gap;

a p-channel split-gate non-volatile memory transistor having a drain coupled to the drain of the split-gate non-volatile memory transistor, a source coupled to a bit line, the source and drain defining a channel, a select gate over a portion of the channel nearest the drain, and a control gate over a non-volatile gate material over a portion of the channel nearest the source, the select gate and the control gate separated by a gap;

a switch transistor having a first source/drain diffusion, a second source/drain diffusion, and a gate coupled to the drains of the n-channel split-gate non-volatile memory transistor and the p-channel split-gate non-volatile memory transistor;

an inverting buffer having an input coupled to the second source/drain diffusion of the switch transistor, and an output;

a p-channel level-restoring transistor having a source coupled to a supply potential, a drain coupled to the first source/drain diffusion of the switch transistor and a gate coupled to the output of the inverting buffer.

6. The split-gate memory cell of claim 5 wherein the non-volatile charge retention structure is a floating gate.

7. The split-gate memory cell of claim 5 wherein the non-volatile charge retention structure is a region of isolated nanocrystals.

8. The split-gate memory cell of claim 5 wherein the non-volatile charge retention structure is a SONOS structure.

9. A split-gate memory cell, including:

a left n-channel split-gate non-volatile memory transistor having a source and a drain, the source and drain defining a channel, a select gate over a portion of the channel nearest the drain, and a control gate over a non-volatile charge retention structure over a portion of the channel nearest the source, the select gate and the control gate separated by a gap;

a right n-channel split-gate non-volatile memory transistor having a source and a drain, the source and drain defining a channel, a select gate over a portion of the channel nearest the drain, and a control gate over a non-volatile gate material over a portion of the channel nearest the source, the select gate and the control gate separated by a gap;

a left p-channel pull-up transistor having a drain coupled to the drain of the left n-channel split-gate non-volatile memory transistor, a source coupled to a left bit line, and a select gate coupled to the drain of the right n-channel split-gate non-volatile memory transistor;

a right p-channel pull-up transistor having a drain coupled to the drain of the right n-channel split-gate non-volatile memory transistor, a source coupled to a left bit line, and a select gate coupled to the drain of the left n-channel split-gate non-volatile memory transistor;

a pass gate including an n-channel pass-gate transistor connected in parallel with a p-channel pass-gate transistor between a switch input node and a switch output node, the n-channel pass-gate transistor having a gate coupled to the gate of a first one of the left and the right p-channel pull-up transistors, the p-channel pass-gate transistor having a gate coupled to the gate of a second one of the left and the right p-channel pull-up transistors.

10. The split-gate memory cell of claim 9 wherein the non-volatile charge retention structure is a floating gate.

11. The split-gate memory cell of claim 9 wherein the non-volatile charge retention structure is a region of isolated nanocrystals.

12. The split-gate memory cell of claim 9 wherein the non-volatile charge retention structure is a SONOS structure.