Hardware extension for accelerating fractional integer division within 3D graphics and MP3 applications
First Claim
1. A data processing apparatus, comprising:
- a random access memory;
a hardware accelerator coupled to said random access memory; and
a digital signal processor (DSP) coupling said hardware accelerator to said random access memory, said hardware accelerator enabling said digital signal processor (DSP) to perform high speed division operations.
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Abstract
An apparatus and method for allowing a digital signal processor (DSP) in a data processing system to perform high speed division operations. In one embodiment of the invention a division operation is performed in no more than two cycles. In another embodiment of the invention, the division operations are in fractional format. The data processing apparatus comprises a random access memory, a processor (12, 168), and an interface (102) coupling said random access memory (104) to said processor, said interface enables high speed division operations associated with said processor. The interface of the present invention can also be combined with a dual or co-processor system to increase the data processing efficiency.
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Citations
13 Claims
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1. A data processing apparatus, comprising:
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a random access memory; a hardware accelerator coupled to said random access memory; and a digital signal processor (DSP) coupling said hardware accelerator to said random access memory, said hardware accelerator enabling said digital signal processor (DSP) to perform high speed division operations. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A data processing apparatus, comprising:
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a random access memory; a hardware accelerator coupled to said random access memory; and a digital signal processor (DSP) coupling said hardware accelerator to said random access memory, said hardware accelerator enabling said digital signal processor (DSP) to perform high speed division operations, wherein said hardware accelerator comprises; a decoder; a first register coupling said decoder to an operator kernel; and a clock controller coupled to said operator kernel.
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9. A telecommunication device, comprising:
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a random access memory; a hardware accelerator coupled to said random access memory; a digital circuitry coupling said hardware accelerator to said random access memory, said hardware accelerator enabling said digital circuitry to perform high speed division operations; analog circuitry; RF circuitry coupling said analog circuitry and said digital circuitry to an antenna; and a power source connected to said RF, analog and digital circuitry. - View Dependent Claims (10, 11, 12)
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13. A method, comprising the steps of:
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providing a processor; and performing a division operation associated with said processor in two cycles, wherein said division operation is enabled by a hardware accelerator, said hardware accelerator comprising; a decoder; a first register coupling said decoder to an operator kernel; and a clock controller coupled to said operator kernel.
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Specification