Instantaneous data-driven clock-gating device and hard-wired streaming processing system including the same

• US 7,694,042 B2
• Filed: 11/03/2006
• Issued: 04/06/2010
• Est. Priority Date: 11/03/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Yong-Ha, Kim, Yun-Kyoung, Lee, Jin-Aeon, Chung, Young-Jin
• Primary Examiner(s): Nguyen; Tanh Q
• Application Number:
  US11/592,123
• Publication Number:
  US 20070174514A1
• Time in Patent Office: 1,250 Days
• Field of Search: None
• US Class Current: 710/52
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing data, a processing unit, and a clock controller circuit. The processing unit may process data from the input FIFO and the clock controller circuit may control a clock signal supplied to the input FIFO and the processing unit. The clock controller circuit may monitor whether there is data to be transferred to the input FIFO and states of the input FIFO and the processing unit and may control the clock signal.

Claims

1. A digital logic processing device comprising:

a first processing element and at least one subsequent processing element, wherein each processing element of the at least one subsequent processing element includes;

an input FIFO for storing data,

a processing unit for processing data from the input FIFO, and

a clock controller circuit for controlling a clock signal supplied to the input FIFO and the processing unit, wherein

the clock controller circuit includes

a detector for detecting an entry into a clock-off state indicating a state of interrupting the clock signal, and for detecting an entry into a clock-on state indicating a state of supplying the clock signal;

a first flip-flop for latching an output of the detector in synchronization with the clock signal;

a second flip-flop for latching an inverted output signal of the first flip-flop in synchronization with an inversion of the clock signal; and

an AND gate for receiving the clock signal and for outputting the clock signal to the input FIFO and the processing unit based on an output of the second flip-flop.

2. The digital logic processing device of claim 1, wherein the clock controller circuit monitors whether there is data to be transferred to the input FIFO, monitors states of the input FIFO and the processing unit, and controls the clock signal.

3. The digital logic processing device of claim 2, wherein the clock controller circuit interrupts the clock signal when the monitorings indicate an idle state.

4. The digital logic processing device of claim 3, wherein the idle state is established when no data to be transferred to the input FIFO exists, the input FIFO is empty, and data from the input FIFO has been processed and has been transferred by the processing unit.

5. The digital logic processing device of claim 4, wherein the clock controller circuit supplies the clock signal to the input FIFO and the processing unit when valid data to be transferred to the input FIFO exists subsequent to the idle state being established.

7. The digital logic processing device of claim 1, wherein the at least one subsequent processing element is a plurality of processing elements configured to operate in a hard-wired streaming processing manner, and in each processing element of the plurality of processing elements,

the input FIFO stores data from a processing element of a previous stage and outputs a first flag signal indicating whether valid data exists;

the processing unit processes data from the input FIFO in response to the first flag signal and outputs a second flag signal indicating whether the data from the input FIFO has been processed and has been transferred; and

the clock controller circuit controls the clock signal to be supplied to the input FIFO and the processing unit in response to a valid signal, the first flag signal and the second flag signal, the valid signal indicating whether valid data to be transferred to the input FIFO exists in the processing unit of the previous stage.

8. The digital logic processing device of claim 7, wherein the clock controller circuit generates a third flag signal indicating a clock off state when a combination of the first and second flag signals indicates an idle state.

9. The digital logic processing device of claim 8, wherein the input FIFO provides the processing unit of the previous stage with information indicating that the input FIFO is not prepared to receive data, in response to the third flag signal.

10. The digital logic processing device of claim 8, wherein the input FIFO of each processing element of the plurality of processing elements acts as an output buffer of a processing element of a previous stage.

11. The digital logic processing device of claim 8, wherein

the detector detects whether a combination of the valid signal and the first and second flag signals indicates the idle state.

12. The digital logic processing device of claim 11, wherein an output signal of the first flip-flop is used as the third flag signal indicating the clock off state.

6. The digital logic processing device of chum 2, wherein the processing unit includes at least one register.