Tagged sequential read operations

• US 7,694,079 B2
• Filed: 04/04/2007
• Issued: 04/06/2010
• Est. Priority Date: 04/04/2007
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Abouelwafa, Ayman
• Primary Examiner(s): Chace; Christian P
• Assistant Examiner(s): Farrokh; Hashem
• Application Number:
  US11/732,621
• Publication Number:
  US 20080250209A1
• Time in Patent Office: 1,098 Days
• Field of Search: 711/137, 711/114
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions

Abstract

In some embodiments, a storage device, comprises a processor, a memory module communicatively connected to the processor, and logic instructions in the memory module which, when executed by the processor, configure the processor to receive a read input/output operation, and configure a prefetch disk data into cache memory in response to a prefetch tag embedded in the read input/output operation.

Claims

1. A method of computing, comprising:

receiving a read input/output operation; and

configuring a prefetch data into cache in response to a prefetch tag embedded in the read input/output operation, a sequential read input/output tag being read from a reserved data block in a SCSI read command.

2. The method of claim 1, wherein configuring a prefetch data into cache in response to a prefetch tag embedded in the read input/output operation comprises prefetching sufficient data for one additional read operation.

3. The method of claim 1, wherein configuring a prefetch cache in response to a prefetch tag embedded in the read input/output operation comprises prefetching sufficient data for between two and eight additional read operations.

4. The method of claim 1, wherein configuring a prefetch data into cache in response to a prefetch tag embedded in the read input/output operation comprises prefetching sufficient data for more than eight additional read operations.

5. The method of claim 1, further comprising:

executing the read input/output operation; and

returning a result of the read input/output operation to a host computer.

6. A method of computing, comprising:

receiving a read input/output operation; and

configuring a prefetch data into cache in response to a prefetch tag embedded in the read input/output operation, a sequential read input/output tag bring read from a reserved data block in a fibre channel frame.

7. The method of claim 6, wherein configuring a prefetch data into cache in response to a prefetch tag embedded in the read input/output operation comprises prefetching sufficient data for one additional read operation.

8. A storage device, comprising:

a processor;

a memory module communicatively connected to the processor;

logic instructions in the memory module which, when executed by the processor, configure the processor to;

receive a read input/output operation; and

configure a prefetch cache in response to a prefetch tag embedded in the read input/output operation, a sequential read input/output tag being read from a reserved data block in a SCSI read command.

9. The storage device of claim 8, further comprising logic instructions in the memory module which, when executed by the processor, configure the processor to prefetch sufficient data for one additional read operation.

10. The storage device of claim 8, further comprising logic instructions in the memory module which, when executed by the processor, configure the processor to prefetch sufficient data for between two and eight additional read operations.

11. The storage device of claim 8, further comprising logic instructions in the memory module which, when executed by the processor, configure the processor to prefetch sufficient data for more than eight additional read operations.

12. The storage device of claim 8, further comprising logic instructions in the memory module which, when executed by the processor, configure the processor to:

execute the read input/output operation; and

return a result of the read input/output operation to a host computer.

13. A storage device, comprising:

a processor;

a memory module communicatively connected to the processor;

logic instructions in the memory module which, when executed by the processor, configure the processor to;

receive a read input/output operation; and

configure a prefetch cache in response to a prefetch tag embedded in the read input/output operation, a sequential read input/output tag being read from a reserved data block in a fibre channel frame.

14. The storage device of claim 13, further comprising logic instructions in the memory module which, when executed by the processor, configure the processor to prefetch sufficient data for one additional read operation.

15. A method, comprising:

generating a read input/output operation in a host computer;

associating a prefetch tag with the read input/output operation;

transmitting the read input/output operation to a storage system;

receiving the read input/output operation in a storage controller in the storage system; and

configuring a prefetch data into cache in response to a prefetch tag embedded in the read input/output operation, a sequential read input/output tag being embedded into a reserved data block in a SCSI read command.

16. The method of claim 15, wherein configuring a prefetch cache in response to a prefetch tag embedded in the read input/output operation comprises prefetching sufficient data for one additional read operation.

17. The method of claim 15, wherein configuring a prefetch cache in response to a prefetch tag embedded in the read input/output operation comprises prefetching sufficient data for between two and eight additional read operations.

18. The method of claim 15, wherein configuring a prefetch cache in response to a prefetch tag embedded in the read input/output operation comprises prefetching sufficient data for more than eight additional read operations.

19. A method, comprising:

generating a read input/output operation in a host computer;

associating a prefetch tag with the read input/output operation;

transmitting the read input/output operation to a storage system;

receiving the read input/output operation in a storage controller in the storage system; and

configuring a prefetch data into cache in response to a prefetch tag embedded in the read input/output operation, a sequential read input/output tag being read from a reserved data block in a fibre channel frame.

20. The method of claim 19, wherein configuring a prefetch cache in response to a prefetch tag embedded in the read input/output operation comprises prefetching sufficient data for one additional read operation.