Systems and methods for CPU repair
First Claim
Patent Images
1. A method for repairing a processor comprising the steps of:
- initializing and executing an operating system on a computer system comprising the processor;
determining that an allocated cache element associated with the processor is faulty;
if a spare cache element is available, swapping in the spare cache element for said faulty allocated cache element during operation of the processor within a clock tick of the operating system while the operating system is executing; and
operating the processor with the swapped-in cache element.
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Abstract
Systems and methods for repairing a processor are provided. In one embodiment, a method for repairing a processor is provided that includes, for example, the steps of initializing and executing an operating system, determining that a cache element is faulty, and swapping in a spare cache element for said faulty cache element while the operating system is executing.
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Citations
36 Claims
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1. A method for repairing a processor comprising the steps of:
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initializing and executing an operating system on a computer system comprising the processor; determining that an allocated cache element associated with the processor is faulty; if a spare cache element is available, swapping in the spare cache element for said faulty allocated cache element during operation of the processor within a clock tick of the operating system while the operating system is executing; and operating the processor with the swapped-in cache element. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A CPU cache element management system comprising:
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at least one CPU of a computer system running an operating system, the CPU having at least one allocated cache element and at least one non-allocated cache element; cache management logic operable to determine whether allocated cache elements are faulty and operable to swap in available said non-allocated cache elements for said allocated cache elements during operation of the CPU within a clock tick of the operating system while the operating system is executing whereby operation of the CPU is maintained with the swapped-in cache elements. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A computer system comprising:
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at least one CPU having at least one allocated cache element and at least one spare cache element; and cache management logic operable to determine whether said at least one allocated cache element is faulty and operable to swap in said at least one available spare cache element for said faulty allocated cache element during operation of the CPU while an operating system is executing on the computer system within a clock tick of the operating system, whereby operation of the CPU is maintained with the swapped-in cache element. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A method for repairing a computer system having an operating system comprising the steps of:
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monitoring at least one cache element associated with at least one CPU for at least one cache error; recording cache error information associated with said at least one cache error; determining whether said at least one cache element is faulty based on said cache error information; determining if at least one spare cache element is available if said at least one cache element is faulty; swapping in said at least one spare cache element during operation of the processor if said at least one spare cache element is available and said at least one cache element is faulty within a clock tick of the operating system while said operating system is running; and operating the processor with the swapped-in cache element. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A processor comprising:
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a plurality of first memory portions; a plurality of second memory portions; logic for determining whether a first memory portion is faulty; and logic for replacing the faulty first memory portion with a selected second memory portion during operation of the processor within a clock tick of an operating system while the operating system is executing, and operating the processor with the selected second memory portion. - View Dependent Claims (28, 29, 30, 31)
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32. A processor comprising:
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a first cache means configured for high-speed information storage and retrieval from the processor; a second cache means for high-speed information storage and retrieval; means for determining whether any portion of the first cache means configured for high-speed information storage is faulty; and means for replacing the faulty portion of the first cache means with an available portion of the second cache means for high-speed information storage and retrieval during operation of the processor within a clock tick of an operating system while the operating system is executing, whereby operation of the processor is maintained with the swapped-in portion of the second cache means. - View Dependent Claims (33, 34, 35, 36)
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Specification