Integrated circuit having built-in self-test features
First Claim
Patent Images
1. A method of built-in self-test in an integrated circuit, comprising:
- communicating a built-in self-test control signal to the integrated circuit;
generating one or more analog self-test signals within the integrated circuit; and
coupling the one or more analog self-test signals to a respective one or more offset control nodes within the integrated circuit in response to the communicating.
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Abstract
An integrated circuit and a method of built-in self test in the integrated circuit employ an offset control node and offset capabilities with the integrated circuit in order to communicate and distribute a built-in self-test signal. The built-in self-test signal can emulate signals internal to the integrated circuit during normal operation, and/or the built-in self-test signal can have other signal characteristics representative of signals other than those signals internal to the integrated circuit during normal operation.
93 Citations
26 Claims
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1. A method of built-in self-test in an integrated circuit, comprising:
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communicating a built-in self-test control signal to the integrated circuit; generating one or more analog self-test signals within the integrated circuit; and coupling the one or more analog self-test signals to a respective one or more offset control nodes within the integrated circuit in response to the communicating. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit, comprising:
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one or more built-in self-test signal generators for generating a respective one or more digital self-test signals; one or more digital-to-analog converters coupled respectively to the one or more built-in self-test signal generators, the one or more digital-to-analog converters for generating a respective one or more analog self-test signals in response to the one or more digital self-test signals; a built-in self-test control node for receiving a built-in self-test control signal; and one or more offset control nodes coupled to receive respectively the one or more analog self-test signals in response to the built-in self-test control signal. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification