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Providing memory test patterns for DLL calibration

  • US 7,694,202 B2
  • Filed: 01/28/2004
  • Issued: 04/06/2010
  • Est. Priority Date: 01/28/2004
  • Status: Expired due to Fees
First Claim
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1. A method of providing a signaling pattern for a bus having a plurality of bit lines, said method comprising:

  • storing a plurality of signals in a serial presence detect circuit;

    transferring said plurality of signals stored in said serial presence detect circuit into a memory controller; and

    for each selected bit line in said plurality of bit lines;

    selecting a first group of at least one of said plurality of signals comprising a set of pseudo-randomly generated bits to be sent over said selected bit line;

    further selecting a second group of at least one of said plurality of signals to be sent over at least one bit line in said plurality of bit lines other than said selected bit line, said selecting and said further selecting being performed by a memory controller from said plurality of signals transferred into said memory controller;

    transmitting said first group of signals on said selected bit line; and

    transmitting said second group of signals over said at least one bit line in said plurality of bit lines other than said selected bit line.

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