Error detection in physical interfaces for point-to-point communications between integrated circuits
First Claim
1. An apparatus for detecting errors in a physical interface that facilitates data communications between integrated circuits (“
- ICs”
), the apparatus comprising;
a decoder configured to decode a subset of encoded data bits to yield decoded data bits, the subset including less than all of the encoded data bits;
a physical interface (“
PI”
) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits, the physical interface error detection bit being used to determine whether the encoded data bits include at least one erroneous data bit as an error; and
an error detector and an error corrector configured to operate within a physical layer, the error detector and error corrector, upon utilizing the physical interface error detection to detect the error within the encoded data bits, to correct the error;
wherein the encoded data bits include an embedded asynchronous clock, the asynchronous clock to be utilized to provide clocking for the encoded data bits upon decoding; and
wherein the subset of the encoded data bits includes N+m data bits and the decoded data bits include N application data bits, where m represents the number of extra bits used for at least embedding the asynchronous clock and the physical interface error detection bit in the encoded data bits.
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Accused Products
Abstract
An apparatus, system and method for detecting errors in a physical interface during the transmission and/or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, an apparatus is configured to operate as or within a receiving physical interface. The apparatus includes a decoder configured to decode a subset of encoded data bits to yield decoded data bits. It also includes a physical interface (“PI”) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits. As such, the apparatus uses the physical interface error detection bit to determine whether the encoded data bits include at least one erroneous data bit as an error. In some embodiments, the apparatus includes an error detector configured to operate within a physical layer. In at least one embodiment, the apparatus efficiently transmits error detection codes within, for example, an NB/(N+1)B line coder.
93 Citations
14 Claims
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1. An apparatus for detecting errors in a physical interface that facilitates data communications between integrated circuits (“
- ICs”
), the apparatus comprising;a decoder configured to decode a subset of encoded data bits to yield decoded data bits, the subset including less than all of the encoded data bits; a physical interface (“
PI”
) error detection bit extractor configured to extract a physical interface error detection bit from the decoded data bits, the physical interface error detection bit being used to determine whether the encoded data bits include at least one erroneous data bit as an error; andan error detector and an error corrector configured to operate within a physical layer, the error detector and error corrector, upon utilizing the physical interface error detection to detect the error within the encoded data bits, to correct the error; wherein the encoded data bits include an embedded asynchronous clock, the asynchronous clock to be utilized to provide clocking for the encoded data bits upon decoding; and wherein the subset of the encoded data bits includes N+m data bits and the decoded data bits include N application data bits, where m represents the number of extra bits used for at least embedding the asynchronous clock and the physical interface error detection bit in the encoded data bits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- ICs”
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11. A method for decoding data bits to at least detect errors at a physical interface, the method comprising:
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decoding a subset of an encoded bit stream having an embedded asynchronous clock to yield decoded data bits, the subset including less than all of the encoded data bits, the asynchronous clock to be utilized to provide clocking for the encoded data bits upon decoding; extracting a physical interface error detection bit from the decoded data bits; determining within a physical layer that the encoded bit stream includes at least one incorrect bit as an error based on the physical interface error detection bit; and correcting the error at the physical interface; wherein determining that the subset of the bit stream includes the incorrect bit comprises; combining the physical interface error detection bit with other physical interface error detection bits to form a first error detection code, generating a second error detection code based on application data bits from the decoded data bits and other application data bits from other decoded data bits decoded from other subsets of the bit stream, comparing the first error detection code against the second error detection code, and determining that the error is present if the second error detection code does not match the first error detection code. - View Dependent Claims (12, 13, 14)
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Specification