Semiconductor integrated circuit, layout method, layout apparatus and layout program

• US 7,694,260 B2
• Filed: 01/10/2006
• Issued: 04/06/2010
• Est. Priority Date: 01/18/2005
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Tamiya, Masayuki
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): Sandoval; Patrick
• Application Number:
  US11/328,075
• Publication Number:
  US 20060157739A1
• Time in Patent Office: 1,547 Days
• Field of Search: 716/7, 716/9, 716/12, 716 19- 21, 716/1, 257/208, 700 90-121, 438 14- 18, 430/5, 430/30, 382141-152, 702108-126
• US Class Current: 716/126
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An intermediate wiring layer, lowermost vias and uppermost vias of a semiconductor integrated circuit are disposed within a zone of wiring tracks, which are superposed by wiring traces of an uppermost wiring layer and wiring traces of a lowermost wiring layer, as seen from the direction normal to the plane. The lowermost vias are disposed so as to fit in a 4-row, 1-column rectangle, and the uppermost vias are disposed so as to fit in a 2-row, 2-column rectangle. The center of a via unit, which comprises the uppermost vias, as seen from the direction normal to the plane is disposed at the intersecting portion of the lowermost wiring layer and uppermost wiring layer. The center of a via unit, which comprises the lower vias, as seen from the direction normal to the plane is offset by a prescribed amount from the center of the via unit, which comprises the uppermost vias, as seen from the direction normal to the plane.

Claims

1. A semiconductor integrated circuit comprising:

a first wiring layer having one pair of wiring traces of first and second potentials that differ from each other;

a second wiring layer disposed in a layer different from said first wiring layer and having one pair of wiring traces of the first and second potentials; and

one or a plurality of intermediate wiring layers disposed between said first wiring layer and said second wiring layer,

wherein the pair of wiring traces of said first wiring layer are disposed in parallel with a prescribed spacing between them,

wherein the pair of wiring traces of said second wiring layer are disposed in parallel with a minimum spacing between them for rendering wiring tracks effective,

wherein the wiring traces of said first wiring layer are in a direction perpendicular to the wiring traces of said second wiring layer,

wherein same-potential wiring traces of said first wiring layer and of said second wiring layer are electrically connected through said intermediate wiring layer and vias,

wherein, as seen from a direction normal to the plane, said intermediate wiring layer is disposed within a zone of wiring tracks superposed by wiring of said first wiring layer and wiring of said second wiring layer,

wherein a number of first vias that connect the wiring of said intermediate wiring layer and the wiring of said first wiring layer is m where m is an integer equal to or greater than 1,

wherein a number of second vias that connect the wiring of said intermediate wiring layer and the wiring of said second wiring layer is m where m is an integer equal to or greater than 1,

wherein the first vias are disposed within a zone of wiring tracks superposed by wiring traces of said second wiring layer and of said first wiring layer as seen from the direction normal to the plane and fit within a rectangular shape of j columns and h rows where j, h are integers equal to or greater than 1 and j×

h≧

m,

wherein the second vias are disposed within a zone of wiring tracks superposed by wiring traces of said second wiring layer and of said first wiring layer as seen from the direction normal to the plane and fit within a rectangular shape of n columns and k rows where n, k are integers equal to or greater than 1 and n×

k≧

m,

wherein the first vias are disposed within an area in which same-potential wiring traces of the wiring of said intermediate wiring layer and the wiring of said first wiring layer overlap,

wherein the second vias are disposed within an area in which same-potential wiring traces of the wiring of said second wiring layer and of the wiring of said first wiring layer overlap,

wherein a center of a via unit for the first potential of via units comprising the second vias, as seen from the direction normal to the plane, is disposed at an intersecting portion of said first wiring layer and said second wiring layer,

wherein a via unit for the first potential of via units comprising the first vias is disposed at a position where it is superimposed at least partially upon the via unit for the first potential of via units comprising the second vias, as seen from the direction normal to the plane, and

wherein a center of the via unit for the first potential of via units comprising the first vias, as seen from the direction normal to the plane, is offset by a prescribed amount from the center of the via unit for the first potential of via units comprising the second vias, as seen from the direction normal to the plane, toward a side of wiring of the second potential in said second wiring layer.

2. The semiconductor integrated circuit according to claim 1, wherein first vias connected to wiring on a side of the first potential and first vias connected to the wiring on the side of the second potential are disposed on same axes, a direction of which is that of wiring of said second wiring layer.

3. The semiconductor integrated circuit according to claim 1, wherein said intermediate wiring layer is disposed such that said intermediate wiring layer overlaps one or both of the pair of wiring traces of said second wiring layer.

4. The semiconductor integrated circuit according to claim 1, wherein said intermediate wiring layer comprises two or more layers,

wherein said intermediate wiring layers are connected by third vias,

wherein the third vias are disposed at positions at which they overlap the first vias as seen from the direction normal to the plane, and

wherein wiring length of whichever of said intermediate wiring layers that immediately underlies said second wiring layer is equal to or greater than a wiring length of whichever of said intermediate wiring layers are other than the intermediate wiring layer that immediately underlies said second wiring layer.

5. The semiconductor integrated circuit according to claim 1, wherein said intermediate wiring layer comprises two or more layers,

wherein said intermediate wiring layers are connected by third vias,

wherein the third vias are disposed at positions at which they overlap the first vias as seen from the direction normal to the plane, and

wherein a wiring width of whichever of said intermediate wiring layers that immediately underlies said second wiring layer is equal to or greater than a wiring width of whichever of said intermediate wiring layers are other than the intermediate wiring layer that immediately underlies said second wiring layer.

6. The semiconductor integrated circuit according to claim 1, wherein said intermediate wiring layer that immediately underlies said second wiring layer is formed in one of a rectangular shape, a T-shaped configuration, and an L-shaped configuration as seen from the direction normal to the plane.

7. The semiconductor integrated circuit according to claim 1, wherein the number of vias that connect the wiring of the first wiring layer and the second wiring layer is an integer equal to or greater than 4,

wherein the vias other than the vias connected to an uppermost wiring layer have been offset to a side of a pair of wiring traces of said uppermost wiring layer by a prescribed amount and are disposed within a zone of wiring tracks superposed by the uppermost wiring layer and a lowermost wiring layer, and

wherein the intermediate wiring layers other than the intermediate wiring layer immediately underlying the uppermost wiring layer are disposed to overlap one or both of the pair of wiring traces of the uppermost wiring layer.

10. The semiconductor integrated circuit according to claim 1, wherein a center of the via unit for a second potential of via units comprising the first vias, as seen from the direction normal to the plane, is offset by a prescribed amount from the center of a via unit for a second potential of via units comprising the second vias, as seen from the direction normal to the plane, toward a side of wiring of the first potential in said second wiring layer.

11. The semiconductor integrated circuit according to claim 1, wherein said first and second wiring layers and said intermediate wiring layers are disposed with a prescribed spacing between them in a direction in which the layers are stacked.

8. A semiconductor integrated circuit, comprising:

an upper and a lower wiring layer, said upper and lower wiring layers comprising a first potential and a second potential;

one or a plurality of intermediate wiring layers;

a set of lower vias of first potential connecting said lower wiring layer to said intermediate wiring layers;

a set of upper vias of first potential connecting an uppermost intermediate wiring layer to said upper wiring layer, and

a center of said set of upper vias of said first potential being disposed at an intersecting portion of said upper wiring layer and said lower wiring layer when seen from a direction normal to the plane,

wherein said set of lower vias of said first potential is disposed at a position where it is superimposed at least partially upon said set of upper vias of said first potential, when seen from the direction normal to the plane, and

wherein said center of said set of lower vias of said first potential is offset by a prescribed amount from said center of said set of upper vias of first potential toward a side of wiring of said second potential in said upper wiring layer when seen from the direction normal to the plane.

9. The semiconductor integrated circuit according to claim 8, wherein said lower and upper wiring layers include a pair of wiring traces of said first potential and said second potential.