Method and apparatus for dynamic frequency voltage switching circuit synthesis
First Claim
1. A computer readable medium storing computer executable instructions for a method useful in synthesis of an integrated circuit, the method comprising:
- using a computer to;
receiving a constraint set for each mode at which a circuit to be synthesized is expected to be operable, each constraint set including a voltage and a frequency corresponding to that voltage;
selecting a voltage as a base mode voltage;
translating frequencies corresponding to voltages different from the base mode voltage into equivalent frequencies, each corresponding to the base mode voltage, and indicative of the relative difficulty to synthesize the circuit to be operable within each constraint set; and
based at least in part on the equivalent frequencies, selecting a constraint set for use in a first synthesis of the circuit.
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Abstract
Methods and apparatus provide for automated synthesis of an integrated circuit whose voltage is varied during operation (also known as dynamic voltage and frequency scaling or DVFS). The automation may include estimating technology parameters from timing libraries, and determining a translation factor that can be used in estimating path delays for an arbitrary voltage from path delays at another voltage. The automation may also include estimating a relative difficulty to synthesize a design for meeting sets of timing constraints specified at different operating voltages and frequencies by assigning one of the constraints a common base value among all the sets, translating the other constraint to maintain equivalency of synthesis difficulty, comparing the resulting equivalent constraints to identify a hardest-to-synthesis constraint set, and using that constraint set as a goal for a first synthesis of the circuit.
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Citations
24 Claims
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1. A computer readable medium storing computer executable instructions for a method useful in synthesis of an integrated circuit, the method comprising:
- using a computer to;
receiving a constraint set for each mode at which a circuit to be synthesized is expected to be operable, each constraint set including a voltage and a frequency corresponding to that voltage; selecting a voltage as a base mode voltage; translating frequencies corresponding to voltages different from the base mode voltage into equivalent frequencies, each corresponding to the base mode voltage, and indicative of the relative difficulty to synthesize the circuit to be operable within each constraint set; and based at least in part on the equivalent frequencies, selecting a constraint set for use in a first synthesis of the circuit. - View Dependent Claims (2, 3, 4, 5, 6)
- using a computer to;
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7. A computer readable medium storing computer executable instructions for a method useful in synthesis of multimode integrated circuits, the method comprising:
- using a computer to;
identifying a first mode and a second mode for operation of an integrated circuit, each of the first mode and the second mode specified by a respective original constraint set comprising at least a first constraint with an original value and a second constraint with an original value; determining a first constraint base value; and for each of the first and second modes with an original first constraint value different from the base value, determining a value for a respective second constraint equivalent that approximately represents, with respect to the first constraint base value, a synthesis constraint equivalent to that provided by the original values of the first constraint and the second constraint for that mode. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
- using a computer to;
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16. A computer readable medium storing computer executable instructions for a method useful in synthesis of integrated circuits, the method comprising:
- using a computer to;
synthesizing a reference integrated circuit based on a component library and for operation at a first voltage and at a second voltage; obtaining respective synthesized delays for each path of a selection of paths in the integrated circuit for circuit operation at each of the first voltage and at the second voltage; determining, for the second voltage, delay estimates for each path of the selection of paths, based at least on the first voltage, a threshold voltage, and a technology-specific parameter a; and selecting values of one or more of the threshold voltage and the parameter a that reduce differences between delay estimates for the second voltage and synthesized delays for the second voltage. - View Dependent Claims (17, 18)
- using a computer to;
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19. A method for synthesis of multimode circuits comprising:
- using a computer to;
receiving sets of constraints for a plurality of operating modes, at which an integrated circuit to be synthesized is to operate, each constraint set including an operating voltage and a maximum path delay; selecting one of the operating voltages as a base mode voltage; translating the maximum path delays of any of the other constraint sets having a voltage different from the base mode voltage into equivalent path delays at the base mode voltage; determining, based at least on the equivalent path delays, a constraint set expected to be hardest to meet during circuit synthesis; and providing for synthesizing the integrated circuit with constraints based on the determined constraint set. - View Dependent Claims (20, 21, 22, 23)
- using a computer to;
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24. A system for synthesis of dynamic voltage and frequency scaling integrated circuits, the system comprising:
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an input configured for receiving a plurality of constraint sets, each constraint set comprising a voltage for operation and a maximum path delay at that voltage; an input configured for receiving a description of a circuit to be synthesized subject to each of the plurality of constraint sets; and a processing resource configured for selecting a voltage of one of the constraint sets as a base voltage, translating maximum path delays for other constraint sets to reference the base voltage while maintaining approximate equivalency of synthesis difficulty for that constraint set, determining, based on the translated maximum path delays, which of the constraint sets will pose the most stringent constraints during synthesis, and providing for first synthesis of the circuit to meet those constraints.
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Specification