Methods for fabricating flash memory devices

• US 7,696,038 B1
• Filed: 04/26/2006
• Issued: 04/13/2010
• Est. Priority Date: 04/26/2006
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Chang, Kuo-Tung, Thurgate, Timothy, Melik-Martirosian, Ashot, Yang, Chih-Yuh, Cheng, Ning, Zheng, Wei, Kinoshita, Hiroyuki, Hui, Angela
• Primary Examiner(s): Andujar, Leonardo
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US11/412,365
• Time in Patent Office: 1,448 Days
• Field of Search: 257/350, 257/686, 257/E21.209, 257/E29.126, 257/E29.137, 438/526, 438/261, 438/248, 438/142, 438/151, 438/231
• US Class Current: 438/231
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

Methods for fabricating flash memory devices are provided. In accordance with an exemplary embodiment of the invention, a method for fabricating a memory device comprises forming a first gate stack and a second gate stack overlying a substrate. A trench is etched into the substrate between the first gate stack and the second gate stack. A first impurity doped region is formed within the substrate underlying the trench.

Claims

1. A method for fabricating a memory device, the method comprising the steps of:

forming a first ONO gate stack and a second ONO gate stack overlying a substrate;

etching a trench into the substrate between the first gate stack and the second gate stack, wherein the trench is etched to a depth in the range of about 100 to about 800 angstroms as measured from a surface of the substrate; and

forming a first impurity doped region within the substrate underlying the trench.

2. The method of claim 1, wherein the step of forming a first impurity doped region comprises the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 2 keV to about 30 keV.

3. The method of claim 2, wherein the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 2 keV to about 30 keV comprises the step of implanting the N-type impurity dopant using an ion implant energy in the range of about 3 keV to about 20 keV.

4. The method of claim 1, further comprising the step of forming gate spacers along sidewalls of the first gate stack and the second gate stack before the step of etching the trench.

5. The method of claim 1, further comprising the step of selectively depositing a mask on the substrate to prevent the formation of a trench at a location where a contact to the substrate is subsequently to be fabricated, wherein the step of selectively depositing is performed before the step of etching a trench.

6. The method of claim 1, further comprising the step of forming a second impurity doped region, wherein the step of forming a second impurity doped region is performed after the step of forming a first gate stack and a second gate stack and before the step of etching a trench.

7. The method of claim 6, wherein the step of forming a second impurity doped region comprises the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 2 keV to about 30 keV.

8. The method of claim 7, wherein the step of forming a first impurity doped region comprises the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 5 keV to about 40 keV.

9. The method of claim 6, further comprising the step of selectively depositing a mask on the substrate to prevent the formation of a trench at a location where a contact to the substrate is subsequently to be fabricated, wherein the step of selectively depositing is performed before the step of etching a trench.

10. The method of claim 1, wherein the step of forming a first gate stack and a second gate stack overlying a substrate comprises the steps of:

fabricating a charge trapping stack on the substrate;

forming a control gate material layer overlying the charge trapping stack;

and etching the control gate material and the charge trapping stack to form the first gate stack and the second gate stack.

11. A method far fabricating a dual bit memory device, the method comprising the steps of:

fabricating a charge trapping ONO stack overlying a substrate;

forming a control gate material overlying the charge trapping stack;

etching the control gate material and the charge trapping stack to the substrate;

etching the substrate to form a trench having a depth in the range of about 100 to about 800 angstroms as measured from a surface of the substrate; and

implanting a first impurity dopant within the substrate underlying the trench to form a first bitline region.

12. The method of claim 11, wherein the step of implanting a first impurity dopant comprises the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 2 keV to about 30 keV.

13. The method of claim 12, wherein the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 2 keV to about 30 keV comprises the step of implanting the N-type impurity dopant using an ion implant energy in the range of about 3 key to about 20 keV.

14. The method of claim 11, further comprising the step of forming gate spacers along sidewalls of the control gate material and the charge trapping stack before the step of etching the trench.

15. The method of claim 11, further comprising the step of selectively depositing a mask on the substrate to prevent the formation of a trench at a location where a contact to the substrate is subsequently to be fabricated, wherein the step of selectively depositing is performed before the step of etching the substrate to form a trench.

16. The method of claim 11, further comprising the step of implanting a second impurity dopant within the substrate to form a second bitline region, wherein the step of implanting a second impurity dopant is performed after the step of etching the control gate material and the charge trapping stack to the substrate and before the step of etching the substrate to form a trench.

17. The method of claim 16, wherein the step of implanting a second impurity dopant comprises the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 2 keV to about 30 keV.

18. The method of claim 17, wherein the step of implanting a first impurity dopant comprises the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 5 key to about 40 keV.

19. The method of claim 16, further comprising the step of selectively depositing a mask on the substrate to prevent the formation of a trench at a location where a contact to the substrate is subsequently to be fabricated, wherein the step of selectively depositing is performed before the step of etching the substrate to form a trench.

20. A method for fabricating a memory device, the method comprising the steps of:

fabricating a first ONO gate stack and a second ONO gate stack overlying a substrate;

forming a first impurity doped region in the substrate between the first gate stack and the second gate stack;

fabricating gate spacers about sidewalls of the first gate stack and the second gate stack after the step of forming the first impurity doped region; and

forming a second impurity doped region in the substrate between the first gate stack and the second gate stack after the step of fabricating the gate spacers, wherein the second impurity doped region is deeper than the first impurity doped region.

21. The method of claim 20, wherein the step of forming a first impurity doped region comprises the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 2 keV to about 30 keV.

22. The method of claim 20, wherein the step of forming a second impurity doped region comprises the step of implanting an N-type impurity dopant using an ion implant energy in the range of about 10 keV to about 50 keV.