Method of manufacturing a trench transistor having a heavy body region

• US 7,696,571 B2
• Filed: 12/05/2008
• Issued: 04/13/2010
• Est. Priority Date: 11/14/1997
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Mo, Brian Sze-Ki, Chau, Duc, Sapp, Steven, Probst, Dean E., Bencuya, Izak
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US12/329,509
• Publication Number:
  US 20090134458A1
• Time in Patent Office: 494 Days
• Field of Search: 257/308, 257/331, 257/341, 257/E29.262, 257/E23.086
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.

Claims

1. A field effect transistor comprising:

a semiconductor substrate having dopants of a first conductivity type;

a trench extending a predetermined depth into the semiconductor substrate, wherein a gate structure is formed inside the trench;

a doped well having dopants of a second conductivity type opposite to the first conductivity type and extending into the semiconductor substrate to form a well junction at a first depth;

a doped source region having dopants of the first conductivity type and extending into the semiconductor substrate to form a source junction at a second depth; and

a doped heavy body region having dopants of the second conductivity type and extending into the doped well to form a heavy body junction at a depth that is deeper than the source junction and shallower than the well junction, the doped heavy body region having a region of high dopant concentration near the junction with the doped well and a region of relatively low dopant concentration near the surface of the substrate, the depth of the doped heavy body region relative to the depth of the doped well is selected so that a peak electric field, when voltage is applied to the transistor, is spaced away from the trench.

2. The field effect transistor of claim 1 wherein an abrupt junction is formed at the interface between the doped heavy body region and the doped well such that, when voltage is applied to the transistor, a peak electric field occurs near the area of the interface.

3. The field effect transistor of claim 1 wherein the doped well has a substantially flat bottom.

4. The field effect transistor of claim 1 wherein the trench has rounded top corners.

5. The field effect transistor of claim 1 wherein the trench has rounded bottom corners.

6. The field effect transistor of claim 1 wherein the trench has rounded top and bottom corners.

7. The field effect transistor of claim 1 wherein the region of high dopant concentration in said doped heavy body region is formed by implanting dopants of the second conductivity type at an approximate location of the junction with the doped well.

8. The field effect transistor of claim 1 wherein the trench is lined with a dielectric material and substantially filled with conductive material, wherein the conductive material substantially filling the trench is recessed relative to the surface of the substrate.

9. The field effect transistor of claim 1 wherein the substrate comprises a first highly doped region and a second doped region disposed above said first highly doped region, the second doped region having a lower doping concentration relative to the first highly doped region.

10. The field effect transistor of claim 9 further comprising a termination structure surrounding the transistor.

11. The field effect transistor of claim 10 wherein the termination structure comprises a doped region having dopants of the second conductivity type extending into the second doped region of the substrate to form a PN junction between the termination doped region and the second doped region of the substrate.

12. The field effect transistor of claim 10 wherein the termination structure comprises a trench.

13. The field effect transistor of claim 10 wherein the termination structure comprises a plurality of concentric trenches surrounding the transistor.

14. The field effect transistor of claim 12 wherein the termination trench extends to substantially the same depth as the transistor trench.

15. The field effect transistor of claim 9 wherein the second doped region of the substrate has an initial thickness of less than 10 μ

m.

16. The field effect transistor of claim 9 wherein the doped well extends into the second doped region of the substrate such that the resulting thickness of the second doped region of the substrate is less than 3 μ

m.

17. The field effect transistor of claim 9 wherein the doped well extends into the second doped region of the substrate such that the resulting thickness of the second doped region of the substrate is approximately 1 μ

m.

18. The field effect transistor of claim 1 wherein the depth of the doped well ranges from approximately 1 to 3 μ

m.

19. The field effect transistor of claim 1 wherein the depth of the doped heavy body ranges from approximately 0.4 μ

m to 1.5 μ

m.

20. The field effect transistor of claim 1 wherein a distance between a bottom of the doped heavy body to the doped well junction ranges from approximately 0.5 μ

m to 1.5 μ

m.

21. The field effect transistor of claim 1 wherein a distance between a bottom of the doped heavy body to the doped well junction is less than approximately 0.5 μ

m.

22. The field effect transistor of claim 1 further comprising a deep doped region having dopants of the second conductivity type, the deep doped region extending into the substrate to a depth below the trench.

23. The field effect transistor of claim 22 wherein said deep doped region forms a PN junction diode with the substrate.

24. The field effect transistor of claim 23 wherein the deep doped region forms a termination structure.