Method and circuit for controlling DC-DC converter

• US 7,696,738 B2
• Filed: 09/14/2007
• Issued: 04/13/2010
• Est. Priority Date: 09/15/2006
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Fujitsu Microelectronics Limited (Fujitsu Limited)
• Inventors: Kato, Kenji, Kasai, Toshihiko, Kokubun, Masatoshi
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US11/898,690
• Publication Number:
  US 20080067989A1
• Time in Patent Office: 942 Days
• Field of Search: 323/282, 323/283, 323/284, 323/285, 323/351
• US Class Current: 323/285
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A DC-DC converter reducing reversed current in a low load state and increasing output voltage response speed. An error amplification circuit generates an error signal from the output voltage. A pulse signal generation circuit generates a first pulse signal in accordance with the error signal. A comparison circuit generates a comparison result signal from the error signal. A drive signal generation circuit generates a constant level signal and a second pulse signal. An output circuit receives the first pulse signal and either the constant level signal or the second pulse signal to generate first and second drive signals for driving first and second transistors. The output circuit generates the second drive signal in accordance with the first pulse signal when receiving the constant level signal and generates the second drive signal with the first and second pulse signals when receiving the second pulse signal.

Claims

1. A DC-DC converter generating an output voltage from an input voltage, the DC-DC converter comprising:

a first transistor receiving the input voltage;

a second transistor coupled to the first transistor;

a choke coil including a first terminal coupled to a connection node between the first and second transistors and a second terminal outputting the output voltage;

an error amplification circuit comparing the output voltage and a first reference voltage to generate an error signal;

a pulse signal generation circuit generating a first pulse signal that is in accordance with the error signal;

a comparison circuit comparing the error signal and a second reference voltage to generate a comparison result signal, the comparison result signal being in either one of a first logic state and a second logic state;

a drive signal generation circuit receiving the comparison result signal and selectively generating either one of a constant level signal and a second pulse signal based on the comparison result signal, with the drive signal generation circuit generating the constant level signal when receiving the comparison result signal in the first logic state and generating the second pulse signal when receiving the comparison result signal in the second logic state; and

an output circuit receiving the first pulse signal and either one of the constant level signal and the second pulse signal and generating first and second drive signals respectively driving the first and second transistors, with the output circuit generating the second drive signal in accordance with the first pulse signal when receiving the constant level signal and generating the second drive signal with the first and second pulse signals when receiving the second pulse signal.

2. The DC-DC converter according to claim 1, wherein the output circuit generates the second drive signal so that the second transistor is activated for a shorter period when receiving the second pulse signal than when receiving the constant level signal.

3. The DC-DC converter according to claim 1, wherein the output circuit generates the second drive signal to intermittently activate the second transistor during inactivation of the first transistor when receiving the second pulse signal.

4. The DC-DC converter according to claim 1, wherein the output circuit generates the second drive signal to drive the second transistor at a first on-duty in a manner complementary to the first transistor when receiving the constant level signal and generates the second drive signal to drive the second transistor at a second on-duty that is smaller than the first on-duty when receiving the second pulse signal.

5. The DC-DC converter according to claim 1, wherein the second pulse signal includes a pulse train synchronized with a clock signal, which is for generating the first pulse signal.

6. The DC-DC converter according to claim 1, further comprising:

a current detection circuit, coupled to the connection node of the first and second transistors and the pulse signal generation circuit, detecting current flowing to the choke coil based on the voltage at the connection node and generating a current detection signal indicating the detection result;

wherein the pulse signal generation circuit includes;

a current comparator comparing the current detection signal and the error signal and generating a current comparison signal indicating the comparison result;

an oscillator generating a clock signal and a synchronization control signal, which has a predetermined pulse train; and

a flip-flop circuit generating the first pulse signal using the current comparison signal and the clock signal; and

the drive signal generation circuit generates the second pulse signal in accordance with the synchronization control signal when receiving the comparison result signal in the second logic state.

7. The DC-DC converter according to claim 6, wherein the oscillator generates the synchronization control signal synchronized with the clock signal.

8. The DC-DC converter according to claim 1, further comprising:

a reversed flow detection circuit detecting reversed current flowing from the choke coil to the second transistor; and

a reversed flow control circuit, coupled to the reversed flow detection circuit and the comparison circuit, preventing reversed current from flowing when the comparison result signal is in the first logic state and allowing reversed current to flow when the comparison result signal is in the second logic state.

9. The DC-DC converter according to claim 8, wherein:

the reversed flow detection circuit includes a comparator, coupled to the second transistor, for detecting reversed current and generating a reversed flow detection signal;

the reversed flow control circuit includes a logic circuit generating a reversed flow control signal with the reversed flow detection signal and the comparison result signal, with the logic circuit generating the reversed flow control signal in accordance with the reversed flow detection signal when the comparison result signal is in the first logic state and generating the reversed flow control signal with a constant level when the comparison result signal is in the second logic state; and

the output circuit generates the second drive signal with the first pulse signal and the reversed flow control signal.

10. The DC-DC converter according to claim 1, further comprising:

a snubber circuit coupled in parallel to the choke coil.

11. The DC-DC converter according to claim 1, wherein the first reference voltage takes an intermediate value in a stable output range of the output voltage, and the second reference voltage takes a value enabling detection of a maximum value of the stable output range of the output voltage.

12. A method controlling a DC-DC converter that generates an output voltage from an input voltage, the DC-DC converter including a first transistor receiving the input voltage, a second transistor coupled to the first transistor, and a choke coil coupled to a connection node between the first and second transistors, the method comprising:

generating an error signal by comparing the output voltage and a first reference voltage;

generating a first pulse signal in accordance with the error signal;

generating a comparison result signal by comparing the error signal and a second reference voltage;

generating a constant level signal when the comparison result signal is in a first logic state;

generating a second pulse signal when the comparison result signal is in a second logic state; and

receiving the first pulse signal and either one of the constant level signal and the second pulse signal; and

generating first and second drive signals respectively driving the first and second transistors, wherein said generating first and second drive signals includes;

generating the second drive signal in accordance with the first pulse signal when the comparison result signal is in the first logic state; and

generating the second drive signal with the first and second pulse signals when the comparison result signal is in the second logic state.

13. The method according to claim 12, wherein said generating the second drive signal with the first and second pulse signals includes generating the second drive signal to intermittently activate the second transistor when the first transistor is inactivated.

14. The method according to claim 12, further comprising:

driving the second transistor at a first on-duty in a manner complementary to the first transistor when the comparison result signal is in the first logic state; and

driving the second transistor at a second on-duty that is smaller than the first on-duty when the comparison result signal is in the second logic state.

15. The method according to claim 12, wherein said generating a second pulse signal includes generating the second pulse signal to have a pulse train synchronized with a clock signal, which is for generating the first pulse signal.

16. The method according to claim 12, wherein:

said generating a first pulse signal includes generating the first pulse signal in accordance with a clock signal; and

said generating a second pulse signal includes generating the second pulse signal in accordance with a synchronization control signal synchronized with the clock signal.

17. The method according to claim 12, further comprising:

detecting reversed current flowing from the choke coil to the second transistor;

preventing reversed current from flowing when the comparison result signal is in the first logic state; and

allowing reversed current to flow when the comparison result signal is in the second logic state.