High current power output stage

• US 7,696,809 B2
• Filed: 09/21/2006
• Issued: 04/13/2010
• Est. Priority Date: 09/29/2005
• Status: Active Grant

• Current Assignee: Continental Automotive GmbH (Continental AG)
• Original Assignee: VDO Automotive AG (Continental AG)
• Inventors: Weiss, Werner, Veit, Claudius
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US11/992,793
• Publication Number:
  US 20090108909A1
• Time in Patent Office: 1,300 Days
• Field of Search: 327/423, 327/424, 327/588, 318/139, 318/430
• US Class Current: 327/423
• CPC Class Codes: H02H 11/002 in case of inverted polarity or connection; with switching for obtaining correct connection
• CPC Class Codes: H02H 7/0838 with H-bridge circuit

Abstract

A high current end power stage comprises at least four power transistors, two electrical supply lines and a safety fuse. The at least four power transistors have each a diode which is blocked during normal operation of the respective power transistor. The two electrical supply lines couple the at least four power transistors with a supply potential and a reference potential such that two of the at least four power transistors are connected electrically between the supply potential and the reference potential. The safety fuse is connected in series to the at least four power transistors in at least one of the two electrical supply lines. The at least one safety fuse can be triggered by a current which flows through the diode of the at least four power transistors, said diode being then arranged in the direction of conduction, when the supply potential and reference potential are exchanged.

Claims

1. A high current power output stage, comprising:

a common carrier;

at least four power transistors, each of the at least four transistors being disposed on a separate semiconductor chip, each of the at least four transistors having a diode which is turned off during a first operating state of the respective power transistor, and each of the semiconductor chips being arranged on the common carrier;

two electrical supply lines coupling the at least four power transistors to a supply potential and a reference potential, at least one of the two electrical supply lines comprises at least one bonding wire, the at least four transistors being connected in series connected pairs between the two electrical supply lines so that each of said pairs is connected in parallel with the others of said pairs;

at least one fusible link connected in series with said at least four power transistors in at least one of said two electrical power supply lines, said fusible link being configured to trigger in response to a current which flows through the diodes of the at least four transistors when the supply potential and the reference potential are reversed; and

at least one additional diode electrically connected in parallel with the series connected pairs of power transistors such that said at least one additional diode is turned off during the first operating state and is in the on state when the supply potential and the reference potential are reversed.

2. A high current power output stage, comprising:

a common carrier;

at least four power transistors, each of the at least four transistors being disposed on a separate semiconductor chip, each of the at least four transistors having a diode which is turned off during a first operating state operation of the respective power transistor, and each of the semiconductor chips being arranged on the common carrier;

two electrical supply lines coupling the at least four power transistors to a supply potential and a reference potential, at least one of the two electrical supply lines comprises at least one bonding wire, the at least four transistors being connected in series connected pairs between the two electrical supply lines so that each of said pairs is connected in parallel with the others of said pairs; and

at least one fusible link connected in series with said at least four power transistors in at least one of said two electrical power supply lines, said fusible link being configured to trigger in response to a current which flows though the diodes of the at least four transistors when the supply potential and the reference potential are reversed, wherein the current is in the range of three to ten times greater than the current flowing through the fusible link during the first operating state operation of the at least four power transistors.