Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
First Claim
1. An integrated circuit comprising:
- a memory array having a respective plurality of array lines of a first type for each of at least one memory layer;
a plurality of I/O bus lines;
a plurality of layer selector circuits, each responsive to an associated enable signal, for coupling respective array lines on an associated memory layer to respective ones of an associated group of said I/O bus lines;
control circuitry for selectively enabling certain layer selector circuits, to simultaneously couple a respective array line to each respective I/O bus line irrespective of whether a second memory layer is implemented, wherein a given I/O bus line is coupled at times to an array line on the first memory layer, and coupled at other times to an array line on the second memory layer if such second memory layer is implemented, and coupled at such other times to an array line on the first memory layer if such second memory layer is not implemented.
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Accused Products
Abstract
An integrated circuit having a three-dimensional memory array provides for a given number of memory planes, but may be fabricated instead to include a lesser number of memory planes by omitting the masks and processing steps associated with the omitted memory planes, without changing any of the other fabrication masks for the other memory planes or for the remainder of the device, and without requiring routing or other configuration changes to the read or read/write path for the array. Control circuitry for selectively enabling certain layer selector circuits is configurable, and the layer selector circuits are suitably arranged, to couple a respective array line on an implemented memory layer to each respective I/O bus line irrespective of the number of implemented memory planes.
73 Citations
19 Claims
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1. An integrated circuit comprising:
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a memory array having a respective plurality of array lines of a first type for each of at least one memory layer; a plurality of I/O bus lines; a plurality of layer selector circuits, each responsive to an associated enable signal, for coupling respective array lines on an associated memory layer to respective ones of an associated group of said I/O bus lines; control circuitry for selectively enabling certain layer selector circuits, to simultaneously couple a respective array line to each respective I/O bus line irrespective of whether a second memory layer is implemented, wherein a given I/O bus line is coupled at times to an array line on the first memory layer, and coupled at other times to an array line on the second memory layer if such second memory layer is implemented, and coupled at such other times to an array line on the first memory layer if such second memory layer is not implemented. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit comprising:
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a memory array having at least one memory layer, each memory layer including a respective plurality of array lines of a first type; means for configuring the memory array depending upon whether a second memory layer is implemented; and means for coupling every respective one of a plurality of I/O bus lines for the memory array to a respective array line irrespective of whether the second memory layer is implemented, wherein a given I/O bus line is coupled at times to an array line on the first memory layer, and coupled at other times to an array line on the second memory layer if such second memory layer is implemented, and coupled at such other times to an array line on the first memory layer if such second memory layer is not implemented.
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9. A method for use in an integrated circuit memory array having at least one memory layer, each memory layer including a respective plurality of array lines of a first type, said method comprising the steps of:
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configuring the memory array depending upon whether a second memory layer is implemented; simultaneously coupling every respective one of a plurality of I/O bus lines for the memory array to a respective array line irrespective of whether the second memory layer is implemented; and coupling a given I/O bus line at times to an array line on the first memory layer, and at other times to an array line on the second memory layer if such second memory layer is implemented, and at such other times to an array line on the first memory layer if such second memory layer is not implemented. - View Dependent Claims (10, 11, 12)
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13. A method for making an integrated circuit product, said method comprising:
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providing a memory array having a respective plurality of array lines of a first type for each of at least one memory layer; providing a plurality of I/O bus lines; providing a plurality of layer selector circuits, each responsive to an associated enable signal, for coupling respective array lines on an associated memory layer to respective ones of an associated group of said I/O bus lines; providing control circuitry for selectively enabling certain layer selector circuits, to simultaneously couple a respective array line to each respective I/O bus line irrespective of whether the second memory layer is implemented, wherein a given I/O bus line is coupled at times to an array line on the first memory layer, and coupled at other times to an array line on the second memory layer if such second memory layer is implemented, and coupled at such other times to an array line on the first memory layer if such second memory layer is not implemented. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification