Multicarrier transmission system with low power sleep mode and rapid-on capability
DCFirst Claim
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1. A method for a multicarrier transceiver to have a low power sleep mode capability comprising:
- during a normal, non-sleep mode operation, receiving a timing reference signal from a FFT at a phase-lock loop (PLL), andlocking the PLL to the timing reference signal; and
during a sleep-mode, where the FFT is dormant;
receiving a timing reference signal from an output of analog-to-digital converter detected by a detector,wherein the timing reference signals are supplied to the PLL based on controller-based switching corresponding to a power mode.
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Abstract
A multicarrier transceiver is provided with a sleep mode in which it idles with reduced power consumption when it is not needed to transmit or receive data. The full transmission and reception capabilities of the transceiver are quickly restored when needed, without requiring the full (and time-consuming) initialization commonly needed to restore such transceivers to operation after inactivity.
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Citations
8 Claims
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1. A method for a multicarrier transceiver to have a low power sleep mode capability comprising:
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during a normal, non-sleep mode operation, receiving a timing reference signal from a FFT at a phase-lock loop (PLL), and locking the PLL to the timing reference signal; and during a sleep-mode, where the FFT is dormant; receiving a timing reference signal from an output of analog-to-digital converter detected by a detector, wherein the timing reference signals are supplied to the PLL based on controller-based switching corresponding to a power mode. - View Dependent Claims (2, 3, 4)
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5. A multicarrier transceiver having a low power sleep mode capability comprising:
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means for, during a normal, non-sleep mode operation, receiving a timing reference signal from a FFT at a phase-lock loop (PLL), and means for locking the PLL to the timing reference signal; and during a sleep-mode, where the FFT is dormant; means for receiving a timing reference signal from an output of analog-to-digital converter detected by a detector, wherein the timing reference signals are supplied to the PLL based on controller-based switching corresponding to a power mode. - View Dependent Claims (6, 7, 8)
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Specification