Parallel data link layer controllers in a network switching device

• US 7,698,412 B2
• Filed: 12/31/2003
• Issued: 04/13/2010
• Est. Priority Date: 12/31/2003
• Status: Expired due to Fees

• Current Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Original Assignee: Alcatel-Lucent SA (Nokia Corporation)
• Inventors: Bailey, John, Narsinh, Anees
• Primary Examiner(s): Neurauter, Jr.; George C
• Assistant Examiner(s): Shin; Kyung H
• Application Number:
  US10/751,129
• Publication Number:
  US 20050198258A1
• Time in Patent Office: 2,295 Days
• Field of Search: 709/232, 709/224, 709/226, 709/239, 370/392, 370/389, 370/230, 370/235
• US Class Current: 709/224
• CPC Class Codes: H04L 12/4666 Operational details on the addition or the stripping of a tag in a frame, e.g. at a provider edge node
• CPC Class Codes: H04L 43/026 using flow identification
• CPC Class Codes: H04L 43/062 related to network traffic
• CPC Class Codes: H04L 43/0888 Throughput
• CPC Class Codes: H04L 43/16 Threshold monitoring
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]
• CPC Class Codes: H04L 49/1523 Parallel switch fabric planes
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/503 Policing

Abstract

The present invention features a data link layer processor for performing VLAN tagging operations, policing, shaping, and statistics acquisition integrally with one or more media access controllers (MACs). When a plurality of data link layer processors are operated in parallel in a switching device, the computational burden carried by the route engine is significantly reduced. Moreover, the data link layer processor in its several embodiments may be used to introduce various forms of pre-processing and post-processing into network switching systems that employ route engines that do not posses such functionality.

Claims

1. A switching device comprising:

one or more physical layer interfaces for receiving one or more frames from a communication network;

a plurality of data link layer processors being coupled to operate in parallel, wherein each data link layer processor comprises;

one or more media access controllers (MACs), wherein each MAC is operatively coupled to a physical layer interface, each of said one or more MACs includes a MAC preprocessor and a MAC postprocessor, said MAC preprocessor including a traffic policer, said traffic policer adapted to execute an ingress traffic policy and frame discard, said traffic policer utilizing a three color marker algorithm to identify frames for discard, wherein the MAC postprocessor includes a traffic shaper adapted to perform bandwidth-based flow control for the egress traffic received by at least one of said MACs, wherein the traffic shaper regulates output bandwidth of the MAC postprocessor using a token bucket algorithm in conjunction with one or more buckets each associated with a respective one of a plurality of flow classes, and wherein tokens allotted to each bucket and tracked using a first counter represent a capacity for each one of said flow classes; and

a statistics acquisition module, operatively coupled to the one or more MACs, for compiling statistics on each of the plurality of MACs; and

a network processor, operatively coupled to the plurality of data link layer processors, for routing the one or more frames received from the plurality of data link layer processors.

2. The switching device of claim 1, wherein each of the data link layer processors further comprises one or more flow search engines for classifying the one or more frames based upon one or more properties associated with the frames.

3. The switching device of claim 2, wherein one or more properties comprise a source port, a VLAN tag state, a VLAN identifier, and a VLAN tag control information (TCI) field.

4. The switching device of claim 2, wherein the one or more flow search engines comprise one or more content addressable memories (CAMs).

5. The switching device of claim 4, wherein the one or more CAMs associated with each of the plurality of data link layer processors consists of QoS rules pertaining to the associated plurality of physical layer interfaces.

6. The switching device of claim 1, wherein data link layer processors are media access controller (MAC) processors.

7. The switching device of claim 1, wherein the switching device is selected from the group consisting of:

a router, a multi-layer switching device, and a switch blade.

8. The switching device of claim 1, wherein the statistics compiled by the statistics acquisition module comprise ingress frame statistics.

9. The switching device of claim 8, wherein the ingress frame statistics are compiled as a function of VLAN entry.

10. The switching device of claim 9, wherein the ingress frame statistics compiled as a function of VLAN entry comprise:

the number of bytes enqueued at the data link layer processor;

the number of frames enqueued at the data link layer processor;

the number of non-unicast bytes enqueued at the data link layer processor; and

the number of non-unicast frames enqueued at the data link layer processor.

11. The switching device of claim 1, wherein the statistics compiled by the statistics acquisition module comprise egress frame statistics.

12. The switching device of claim 11, wherein egress frame statistics are compiled as a function of physical layer interface.

13. The switching device of claim 12, wherein egress frame statistics are further compiled as a function of VLAN entry.

14. The switching device of claim 1, wherein said MAC preprocessor includes at least one of a MAC buffer, a VLAN push module, a rate buffer, and an ingress bus transmitter.

15. The switching device of claim 1, wherein said MAC postprocessor includes at least one of an egress bus receiver, a rate buffer, and a VLAN pop module.

16. The switching device of claim 1, wherein said traffic policer includes a parser for inspecting the received one or more frames.

17. The switching device of claim 16, wherein said traffic policer includes a flow search engine for classifying the one or more frames based upon one or more properties associated with the frames.

18. The switching device of claim 17, wherein the flow search engine comprises content addressable memories (CAMs).