Switching apparatus and method for link initialization in a shared I/O environment

• US 7,698,483 B2
• Filed: 10/25/2004
• Issued: 04/13/2010
• Est. Priority Date: 01/21/2003
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: NextIO Incorporated
• Inventors: Khan, Asif, Pagan, Annette, Utley, Robert Haskell, Pekkala, Richard E., Pettey, Christopher J.
• Primary Examiner(s): Hafiz; Tariq R.
• Assistant Examiner(s): SUN, SCOTT C
• Application Number:
  US10/972,669
• Publication Number:
  US 20050102437A1
• Time in Patent Office: 1,996 Days
• Field of Search: None
• US Class Current: 710/62
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An apparatus has a first plurality of I/O ports, a second I/O port, and link training logic. The first plurality is coupled to a plurality of operating system domains through a load-store fabric. Each of the first plurality is configured to route transactions between the plurality of operating system domains and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint is configured to request/complete the transactions for each of the plurality of operating system domains. The link training logic is coupled to the second I/O port. The link training logic initializes a link between the second I/O port and the first shared input/output endpoint to support the transactions corresponding to the each of the plurality of operating system domains. The link is initialized in a manner that is transparent to the plurality of operating system domains.

Claims

1. A switching apparatus for sharing input/output endpoints, the switching apparatus comprising:

a first plurality of I/O ports, coupled to a plurality of operating system domains through a load-store fabric, each configured to route transactions between said plurality of operating system domains and the switching apparatus;

a second I/O port, coupled to a first shared input/output endpoint, wherein said first shared input/output endpoint is configured to request/complete said transactions for each of said plurality of operating system domains according to a variant of a protocol, wherein said variant comprises encapsulating an OS domain header within a transaction layer packet that otherwise comports with said protocol, and wherein a particular OS domain header associates a particular transaction layer packet with a particular one of said plurality of operating system domains; and

link training logic, coupled to said second I/O port, configured to initialize a link between said second I/O port and said first shared input/output endpoint to support said transactions corresponding to said each of said plurality of operating system domains, wherein said link is initialized in a manner that is transparent to said plurality of operating system domains.

2. The switching apparatus as recited in claim 1, wherein the switching apparatus routes said transactions according to said protocol that provides for routing of said transactions only for a single operating system domain, and wherein said first plurality of I/O ports communicates with said plurality of operating system domains according to said protocol.

3. The switching apparatus as recited in claim 2, wherein said link training logic employs a mechanism according to said protocol to initialize said link, and wherein said mechanism would otherwise be ignored by a non-shared input/output endpoint, and wherein said first shared input/output endpoint recognizes said mechanism.

4. The switching apparatus as recited in claim 3, wherein said first shared input/output endpoint provides a count to said second I/O port indicating a number of said plurality of operating system domains that said first shared input/output endpoint is capable of supporting.

5. The switching apparatus as recited in claim 3, wherein said protocol comprises the PCI Express protocol, and wherein said mechanism comprises a PCI Express data link layer packet that is undefined.

6. The switching apparatus as recited in claim 2, further comprising:

a third I/O port, coupled to a non-shared input/output endpoint and said link training logic, wherein said link training logic is configured to initialize a second link between said third I/O port and said non-shared input/output endpoint to support one of said plurality of operating system domains, and wherein said link training logic attempts to initialize said second link by employing a first mechanism according to said protocol to initialize said second link, and wherein said first mechanism is ignored by said non-shared input/output endpoint, and wherein said link training logic completes initialization of said second link by employing a second mechanism according to said protocol which is accepted by said non-shared input/output endpoint.

7. The switching apparatus as recited in claim 1, further comprising:

core logic, coupled to said first plurality of I/O ports and said second I/O port, configured to route said transactions between said first plurality of I/O ports and said second I/O port, wherein said core logic maps said each of said plurality of operating system domains to a corresponding root complex.

8. The switching apparatus as recited in claim 7, wherein said corresponding root complex is associated with one or more processing complexes, each comprising:

a processing core, configured to process data, wherein said processing core accesses a memory that is configured to store said data.

9. The switching apparatus as recited in claim 7, wherein said core logic is configured to associate each of said transactions with a corresponding one of said plurality of operating system domains (OSDs), said corresponding one of said plurality of OSDs corresponding to one or more root complexes.

10. The switching apparatus as recited in claim 1, wherein said link is initialized without any intervention by system software.

11. The switching apparatus as recited in claim 10, wherein said system software comprises operating systems, basic input/output systems (BIOS), configuration applications, and management applications.

12. A shared input/output (I/O) switching mechanism, comprising:

a first plurality of I/O ports, coupled to a plurality of operating system domains through a load-store fabric, each configured to route transactions between said plurality of operating system domains and the shared input/output (I/O) switching mechanism;

a second I/O port, coupled to a first shared input/output endpoint, wherein said first shared input/output endpoint is configured to request/complete said transactions for each of said plurality of operating system domains according to a variant of a protocol, wherein said variant comprises encapsulating an OS domain header within a transaction layer packet that otherwise comports with said protocol, and wherein a particular OS domain header associates a particular transaction layer packet with a particular one of said plurality of operating system domains;

core logic, coupled to said first plurality of I/O ports and said second I/O port, configured to route said transactions between said first plurality of I/O ports and said second I/O port, wherein said core logic maps said each of said plurality of operating system domains to a corresponding root complex; and

link training logic, coupled to said second I/O port, configured to initialize a link between said second I/O port and said first shared input/output endpoint to support said transactions corresponding to said each of said plurality of operating system domains, wherein said link is initialized in a manner that is transparent to said plurality of operating system domains.

13. The shared I/O switching mechanism as recited in claim 12, wherein the shared I/O switching mechanism routes said transactions according to said protocol that provides for routing of said transactions only for a single operating system domain, and wherein said first plurality of I/O ports communicates with said plurality of operating system domains according to said protocol.

14. The shared I/O switching mechanism as recited in claim 13, wherein said link training logic employs a mechanism according to said protocol to initialize said link, and wherein said mechanism would otherwise be ignored by a non-shared input/output endpoint, and wherein said first shared input/output endpoint recognizes said mechanism.

15. The shared I/O switching mechanism as recited in claim 14, wherein said first shared input/output endpoint provides a count to said second I/O port indicating a number of said plurality of operating system domains that said first shared input/output endpoint is capable of supporting.

16. The shared I/O switching mechanism as recited in claim 14, wherein said protocol comprises the PCI Express protocol, and wherein said mechanism comprises a PCI Express data link layer packet that is undefined.

17. The shared I/O switching mechanism as recited in claim 13, further comprising:

a third I/O port, coupled to a non-shared input/output endpoint and said link training logic, wherein said link training logic is configured to initialize a second link between said third I/O port and said non-shared input/output endpoint to support one of said plurality of operating system domains, and wherein said link training logic attempts to initialize said second link by employing a first mechanism according to said protocol to initialize said second link, and wherein said first mechanism is ignored by said non-shared input/output endpoint, and wherein said link training logic completes initialization of said second link by employing a second mechanism according to said protocol which is accepted by said non-shared input/output endpoint.

18. The shared I/O switching mechanism as recited in claim 12, wherein said corresponding root complex is associated with one or more processing complexes, each comprising:

a processing core, configured to process data, wherein said processing core accesses a memory that is configured to store said data.

19. The shared I/O switching mechanism as recited in claim 18 wherein said core logic is configured to associate each of said transactions with a corresponding one of said plurality of operating system domains (OSDs), said corresponding one of said plurality of OSDs corresponding to one or more root complexes.

20. The shared I/O switching mechanism as recited in claim 12, wherein said link is initialized without any intervention by system software.

21. The shared I/O switching mechanism as recited in claim 20, wherein said system software comprises operating systems, basic input/output systems (BIOS), configuration applications, and management applications.

22. A method for interconnecting independent operating system domains to a shared I/O endpoint within a load-store fabric, comprising:

via first ports, first communicating with each of the independent operating system domains according to a protocol that provides exclusively for a single operating system domain within the load-store fabric;

via a second port, second communicating with the shared I/O endpoint according to a variant of the protocol to enable the shared I/O endpoint to associate a prescribed operation with a corresponding one of the independent operating system domains, wherein the variant comprises encapsulating an OS domain header within a transaction layer packet that otherwise comports with the protocol, and wherein a particular OS domain header associates the transaction layer packet with the corresponding one of the independent operating system domains; and

initializing a link between the second port and the shared I/O endpoint to support transactions for all of the independent operating system domains, wherein the link is initialized in a manner that is transparent to the independent operating system domains.

23. The method as recited in claim 22, wherein said initializing comprises:

employing a mechanism according to the protocol to initialize the link, wherein the mechanism would otherwise be ignored by a non-shared input/output endpoint, and wherein the shared input/output endpoint recognizes the mechanism.

24. The method as recited in claim 22, wherein said initializing comprises:

via a count provided by the shared input/output endpoint, indicating a number of operating system domains that the shared input/output endpoint is capable of supporting.

25. The method as recited in claim 23, wherein the protocol comprises the PCI Express protocol, and wherein the mechanism comprises a PCI Express data link layer packet that is undefined.

26. The method as recited in claim 22, further comprising:

attempting to initialize a second link between a third port and a non-shared I/O endpoint, the third I/O endpoint supporting transactions for one of the independent operation system domains, wherein said attempting comprises employing the variant of the protocol to initialize said second link, and wherein the variant of the protocol is ignored by the non-shared input/output endpoint; and

completing initialization of the second link by according to the protocol.

27. The method as recited in claim 22, further comprising:

via core logic, mapping the independent operating system domains to the shared I/O endpoint.

28. The switching apparatus as recited in claim 22, wherein the link is initialized without any intervention by system software.

29. The switching apparatus as recited in claim 28, wherein the system software comprises operating systems, basic input/output systems (BIOS), configuration applications, and management applications.