Dynamic hardware multithreading and partitioned hardware multithreading
First Claim
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1. A method for dynamic enabling or disabling of hardware multithreading on a processor core, the method comprising:
- using a hardware halt function or a hardware yield function in the processor core in order to enable or disable a first hardware thread that shares the processor core, wherein the first hardware thread is disabled by placing the first hardware thread in a halt state or yield state;
allowing a second hardware thread to utilize the processor core; and
in addition to placing the first hardware thread in the halt or yield state, removing the first hardware thread from a view of an operating system by removing information associated with the first hardware thread from at least one data structure associated with the operating system, wherein placing the first hardware thread in the halt state or yield state and removing the first hardware thread from the view of the operating system cause disabling of the hardware multithreading on the processor core, andenabling hardware multithreading on the processor core by removing the first hardware thread from the halt state or yield state and placing the first hardware thread in the view of the operating system by retrieving information associated with the first hardware thread into the at least one data structure associated with the operating system,wherein using the hardware halt function or the hardware yield function permits multithreading enabling and disabling on hardware that does not support dynamic enabling and disabling of hardware threads without operating system reboot or system reset.
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Abstract
In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.
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18 Claims
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1. A method for dynamic enabling or disabling of hardware multithreading on a processor core, the method comprising:
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using a hardware halt function or a hardware yield function in the processor core in order to enable or disable a first hardware thread that shares the processor core, wherein the first hardware thread is disabled by placing the first hardware thread in a halt state or yield state; allowing a second hardware thread to utilize the processor core; and in addition to placing the first hardware thread in the halt or yield state, removing the first hardware thread from a view of an operating system by removing information associated with the first hardware thread from at least one data structure associated with the operating system, wherein placing the first hardware thread in the halt state or yield state and removing the first hardware thread from the view of the operating system cause disabling of the hardware multithreading on the processor core, and enabling hardware multithreading on the processor core by removing the first hardware thread from the halt state or yield state and placing the first hardware thread in the view of the operating system by retrieving information associated with the first hardware thread into the at least one data structure associated with the operating system, wherein using the hardware halt function or the hardware yield function permits multithreading enabling and disabling on hardware that does not support dynamic enabling and disabling of hardware threads without operating system reboot or system reset. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus for dynamic enabling or disabling of hardware multithreading, the apparatus comprising:
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a computer system including a processor and an operating system; wherein the processor includes a processor core with a hardware halt function or a hardware yield function that is invoked for enabling and disabling a first hardware thread that shares the processor core, and wherein the first hardware thread is disabled by placing the first hardware thread in a halt state or yield state, and wherein a second hardware thread is allowed to utilize the processor core, wherein the first hardware thread is further removed from a view of the operating system by removing information associated with the first hardware thread from at least one data structure associated with the operating system, wherein placing the first hardware thread in the halt state or yield state and removing the first hardware thread from the view of the operating system cause disabling of the hardware multithreading on the processor core, wherein the hardware multithreading is enabled on the processor core by removing the first hardware thread from the halt state or yield state and by placing the first hardware thread in the view of the operating system by retrieving information associated with the first hardware thread into the at least one data structure, and wherein using the hardware halt function or the hardware yield function permits multithreading enabling and disabling on hardware that does not support dynamic enabling and disabling of hardware threads without system reset or operating system reboot. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification