Method and apparatus for timing and event processing in wireless systems
First Claim
1. A digital baseband processor comprising:
- at least one main processor for executing instructions in a first instruction sequence; and
a timing and event processor coupled to said main processor for executing timing-sensitive instructions in a second instruction sequence, said timing and event processor comprising;
two or more instruction sequencers for executing threads of the second instruction sequence; and
a time base generator for generating timing signals for initiating execution of instructions on each of the two or more instruction sequencers, wherein said time base generator is configured to use a unified time base derived from a plurality of time bases.
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Accused Products
Abstract
A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and a timing and event processor controlled by the digital signal processor and the microcontroller for executing timing-sensitive instructions. The timing and event processor includes a plurality of instruction sequencers for executing timing-sensitive instruction threads and a time base generator for generating timing signals for initiating execution of the instruction threads on each of the plurality of instruction sequencers.
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Citations
22 Claims
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1. A digital baseband processor comprising:
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at least one main processor for executing instructions in a first instruction sequence; and a timing and event processor coupled to said main processor for executing timing-sensitive instructions in a second instruction sequence, said timing and event processor comprising; two or more instruction sequencers for executing threads of the second instruction sequence; and a time base generator for generating timing signals for initiating execution of instructions on each of the two or more instruction sequencers, wherein said time base generator is configured to use a unified time base derived from a plurality of time bases. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method for operating a digital baseband processor, comprising:
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providing a digital baseband processor including a main processor and a timing and event processor coupled to the main processor, the timing and event processor including two or more instruction sequencers and a time base generator configured to use a unified time base derived from a plurality of time bases; executing instructions of a first instruction sequence in the main processor; and executing timing-sensitive instructions of a second instruction sequence in the timing and event processor, including executing threads of the second instruction sequence in the two or more instruction sequencers and generating timing signals in the time base generator for initiating execution of instructions on each of the two or more instruction sequencers. - View Dependent Claims (18, 19, 20, 21, 22)
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Specification