Method and design system for semiconductor integrated circuit with a reduced placement area

• US 7,698,675 B2
• Filed: 10/17/2006
• Issued: 04/13/2010
• Est. Priority Date: 10/18/2005
• Status: Expired due to Fees

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Kitano, Tomohiro
• Primary Examiner(s): Siek; Vuthe
• Application Number:
  US11/581,756
• Publication Number:
  US 20070089083A1
• Time in Patent Office: 1,274 Days
• Field of Search: 716/2, 716 7- 14
• US Class Current: 716/124
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A standard cell is split into a plurality of regions, and shareability information having pin information is added to a cell library for each of the split regions. Through comparison of shareability information, a determination is made as to whether, at the time of automatic placement, a standard cell can be placed so as to share part of its region with a standard cell placed adjacent to that standard cell. On the basis of the determination result, when placing a standard cell, a standard cell to be placed adjacent to that standard cell is placed so as to share part of its region, thereby making it possible to reduce the placement area.

Claims

1. A method of designing a semiconductor device, comprising:

preparing, by a computer processor, a plurality of cells, each of the cells being configured by splitting a pattern layout of each cell into at least a first side region on a first side of each cell and a second side region on a second side of each cell and by further splitting each of the first and second side regions into first, second and third sub-regions, the first, second and third sub-regions being labeled by respective pin names;

placing, by the computer processor, based on circuit information in which an output of a first cell is connected to an input of a second cell, the first cell and the second cell of the cells adjacently to each other such that the pin names of the first and third sub-regions of the second side region of the first cell are identical respectively to the pin names of the first and third sub-regions of the first side region of the second cell and the pin name of the second sub-region of the second side region of the first cell and the pin name of the second sub-region of the first side region of the second cell are respectively the output of the first cell and the input of the second cell; and

sharing, by the computer processor, the first, second and third sub-regions of the second side region of the first cell respectively with the fist, second and third sub-regions of the first side region of the second cell.

2. The method as claimed in claim 1, wherein the first, second and third sub-regions of each of the first and second regions of each of the first and second cells are a PMOS region, an isolation region, and an NMOS region, respectively.

3. The method as claimed in claim 1, further comprising:

placing, by the computer processor, a third cell of the cells adjacently to the second cell on an opposite side to the first cell; and

sharing, by the computer processor, the first and third sub-regions of the second side region of the second cell respectively with the first and third sub-regions of the first side region of the third cell.

4. The method as claimed in claim 3, wherein the second region of the second side region of the second cell serves as an output of the second cell and is shared with the second sub-region of the first side region of the third cell serving as an input of the third cell.

5. A method of designing a semiconductor device, comprising:

preparing, by a computer processor, first and second inverter cells, the first inverter cell including first and second P-type regions, a first gate electrode formed between the first and second P-type regions, first and second N-type regions, a second gate electrode formed between the first and second N-type regions, and a first conductive line connecting the first P-type region and the first N-type region to each other with crossing over the first and second gate electrodes, the second inverter cell including third and fourth P-type regions, a third gate electrode formed between the third and fourth P-type regions, third and fourth N-type regions, a fourth gate electrode formed between the third and fourth N-type regions, and a second conductive line connecting the third P-type region and the third N-type region to each other without crossing over the first and second gate electrodes;

locating, by the computer processor, the first and second inverter cells such that the second P-type region and the second N-type region of the first inverter cell are adjacently respectively to the fourth P-type region and the fourth N-type region of the second inverter cell; and

sharing, by the computer processor, the second P-type region and the second N-type region of the first inverter cell respectively with the fourth P-type region and the fourth N-type region of the second inverter cell to prove a shared P-type region and a shared N-type region.

6. The method as claimed in claim 5, further comprising connecting the first conductive line to each of the third and fourth gate electrodes of the second inverter cell.

7. The method as claimed in claim 6, further comprising connecting a first power supply line to the shared P-type region and a second power supply line to the shared N-type region.

8. The method as claimed in claim 5, further comprising:

preparing, by the computer processor, a transfer gate cell, the transfer gate cell including fifth and sixth P-type regions, a fifth gate electrode formed between the fifth and sixth P-type regions, fifth and sixth N-type regions, a sixth gate electrode formed between the fifth and sixth N-type regions, a third conductive line connecting the fifth P-type region and the fifth N-type region to each other, and a fourth conductive line connecting the sixth P-type region and the sixth N-type region to each other;

locating, by the computer processor, the transfer gate such that the third P-type region and the third N-type region of the second inverter cell are adjacent respectively to the fifth P-type region and the fifth N-type region of the transfer gate cell; and

connecting, by the computer processor, the second conductive line of the second inverter cell to the third conductive line of the transfer gate cell.

9. The method as claimed in claim 5, further comprising:

preparing, by the computer processor, a transfer gate cell, the transfer gate cell including fifth and sixth P-type regions, a fifth gate electrode formed between the fifth and sixth P-type regions, fifth and sixth N-type regions, a sixth gate electrode formed between the fifth and sixth N-type regions, a third conductive line connecting the fifth P-type region and the fifth N-type region to each other, and a fourth conductive line connecting the sixth P-type region and the sixth N-type region to each other;

locating, by the computer processor, the transfer gate such that the third P-type region and the third N-type region of the second inverter cell are adjacent respectively to the fifth P-type region and the fifth N-type region of the transfer gate cell; and

sharing, by the computer processor, the third P-type region and the third N-type region of the second inverter cell respectively with the fifth P-type region and the fifth N-type region of the transfer gate cell.

10. A method of designing a semiconductor device, comprising:

preparing, by a computer processor, a cell library including an inverter cell, the inverter cell including first and second P-type regions, a first gate electrode formed between the first and second P-type regions, first and second N-type regions, a second gate electrode formed between the first and second N-type regions, and a first conductive line connecting the first P-type region and the first N-type region to each other without crossing over the fist and second gate electrodes;

reading, by the computer processor, the inverter cell from the cell library twice to provide first and second inverter cells;

locating, by the computer processor, the first and second inverter cells such that the second P-type region and the second N-type region of the first inverter cell are adjacent respectively to the second P-type region and the second N-type region of the second inverter cell; and

sharing, by the computer processor, the second P-type region and the second N-type region of the first inverter cell respectively with the second P-type region and the second N-type region of the second inverter cell to prove a first shared P-type region and a first shared N-type region.

11. The method as claimed in claim 10, further comprising connecting a first power supply line to the first shared P-type region and a second power supply line to the first shared N-type region.

12. The method as claimed in claim 10, wherein the cell library further includes a transfer gate cell, the transfer gate cell including third and fourth P-type regions, a third gate electrode formed between the third and fourth P-type regions, third and fourth N-type regions, a fourth gate electrode formed between the third and fourth N-type regions, a second conductive line connecting third P-type region and third N-type region to each other, and a third conductive line connecting the fourth P-type region and the fourth N-type region to each other, and the method further comprises:

locating, by the computer processor, the transfer gate cell such that the third P-type region and the third N-type region of the transfer gate cell are adjacent respectively with the first P-type region and the first N-type region of the second inverter cell; and

sharing, by the computer processor, the third P-type region and the third N-type region of the transfer gate cell are adjacent respectively with the first P-type region and the first N-type region of the second inverter cell to prove a second shared P-type region and a second shared N-type region, the second conductive line being thereby connecting the second shared P-type region and the second shared N-type region to each other.