Stacked bit line dual word line nonvolatile memory

• US 7,700,415 B2
• Filed: 07/31/2008
• Issued: 04/20/2010
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lung, Hsiang-Lan
• Primary Examiner(s): Booth; Richard A.
• Application Number:
  US12/184,181
• Publication Number:
  US 20080286906A1
• Time in Patent Office: 628 Days
• Field of Search: 438/132, 438257-267, 438/460
• US Class Current: 438/131
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Claims

1. A method of fabricating an arrangement of nonvolatile memory devices, the method comprising:

(a) providing a semiconductor substrate;

(b) forming an oxide layer;

(c) forming a plurality of word lines substantially disposed above the oxide layer;

(d) forming a plurality of bit lines substantially disposed above the oxide layer;

(e) etching a plurality of via holes formed between the plurality of word lines and the plurality of bit lines substantially in contact with the plurality of word lines and the plurality of bit lines; and

(f) forming an anti-fuse dielectric material substantially disposed beside the plurality of bit lines and substantially in electrical contact with the plurality of bit lines, the anti-fuse dielectric material forming a plurality of side wall anti-fuse dielectrics beside the bit lines;

(g) forming a plurality of via plugs substantially in electrical contact with the plurality of word lines and substantially in contact with the plurality of side wall anti-fuse dielectrics.

2. The method of fabricating an arrangement of nonvolatile memory devices according to claim 1, wherein the bit lines are formed from polysilicon having a first type of background impurity and the via plugs are formed from polysilicon having a second type of background impurity opposite to the first type.

3. The method of fabricating an arrangement of nonvolatile memory devices according to claim 2, wherein the first type of background impurity is N-type and the second type of background impurity is P-type.

4. The method of fabricating an arrangement of nonvolatile memory devices according to claim 2, wherein the first type of background impurity is P-type and the second type of background impurity is N-type.

5. The method of fabricating an arrangement of nonvolatile memory devices according to claim 1, wherein the step of forming a plurality of word lines further comprises the step of forming a plurality of pairs of word lines.

6. The method of fabricating an arrangement of nonvolatile memory devices according to claim 5, wherein the pairs of word lines are disposed on different horizontal planes.

7. The method of fabricating an arrangement of nonvolatile memory devices according to claim 6, wherein the bit lines are formed from polysilicon having a first type of background impurity and the via plugs are formed from polysilicon having a second type of background impurity opposite to the first type.

8. The method of fabricating an arrangement of nonvolatile memory devices according to claim 7, wherein the first type of background impurity is N-type and the second type of background impurity is P-type.

9. The method of fabricating an arrangement of nonvolatile memory devices according to claim 7, wherein the first type of background impurity is P-type and the second type of background impurity is N-type.