Raised source drain mosfet with amorphous notched gate cap layer with notch sidewalls passivated and filled with dielectric plug
First Claim
1. An improvement in a method of forming a MOSFET device, said MOSFET device including a semiconductor substrate with a silicon surface, with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on said silicon surface, with the gate electrode stack comprising a gate electrode formed of gate polysilicon formed over a gate dielectric layer formed on said silicon surface, said gate polysilicon having a top;
- said method comprising the steps preformed in the sequence as follows;
forming a cap layer composed of amorphous silicon on said top of said gate electrode layer;
forming a patterned mask for patterning said gate electrode stack over said cap layer with said mask covering a portion of said cap layer;
performing an etching process undercutting said cap layer peripherally under said mask thereby forming a notch in said cap layer below said mask with said notch having notch sidewalls;
passivating said notch sidewalls;
patterning said gate electrode stack in said pattern of said mask with an etching process;
filling said notch with dielectric plugs formed of sidewall spacer material on sidewalls of said gate polysilicon with said dielectric plugs and sidewall spacers covering sidewalls of said gate with forming said sidewall spacers reaching along the sidewalls of the gate electrode stack to above the level where said plugs contact said gate polysilicon; and
forming raised source/drain regions on top of said silicon surface aside from said sidewall spacers,whereby formation of spurious epitaxial growth of silicon nodules on said sidewalls of said gate dielectric during the formation of raised source/drain regions is avoided.
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Accused Products
Abstract
A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A thin amorphous silicon cap layer is formed in the top surface of the gate electrode by implanting dopant into the surface thereof. A notch is etched into the periphery of the cap layer. A plug of dielectric material is formed in the notch. The sidewalls of the gate electrode are covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.
13 Citations
16 Claims
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1. An improvement in a method of forming a MOSFET device, said MOSFET device including a semiconductor substrate with a silicon surface, with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on said silicon surface, with the gate electrode stack comprising a gate electrode formed of gate polysilicon formed over a gate dielectric layer formed on said silicon surface, said gate polysilicon having a top;
- said method comprising the steps preformed in the sequence as follows;
forming a cap layer composed of amorphous silicon on said top of said gate electrode layer; forming a patterned mask for patterning said gate electrode stack over said cap layer with said mask covering a portion of said cap layer; performing an etching process undercutting said cap layer peripherally under said mask thereby forming a notch in said cap layer below said mask with said notch having notch sidewalls; passivating said notch sidewalls; patterning said gate electrode stack in said pattern of said mask with an etching process; filling said notch with dielectric plugs formed of sidewall spacer material on sidewalls of said gate polysilicon with said dielectric plugs and sidewall spacers covering sidewalls of said gate with forming said sidewall spacers reaching along the sidewalls of the gate electrode stack to above the level where said plugs contact said gate polysilicon; and forming raised source/drain regions on top of said silicon surface aside from said sidewall spacers, whereby formation of spurious epitaxial growth of silicon nodules on said sidewalls of said gate dielectric during the formation of raised source/drain regions is avoided. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- said method comprising the steps preformed in the sequence as follows;
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11. An improvement in a method of forming a MOSFET device comprising the steps performed in the order as follows:
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form a semiconductor substrate having an upper semiconductor surface; form a gate dielectric layer on said upper semiconductor surface; form a polysilicon layer over said gate dielectric layer having an upper polysilicon surface; implant ions into said upper polysilicon surface of said polysilicon layer forming an amorphous layer in said surface of said polysilicon layer; form a mask over said polysilicon layer; etch to form a notch with notch sidewalls recessed in sidewalls of said top surface of said gate electrode below said mask; then passivate said notch sidewalls by growing a silicon oxide layer thereon; perform a short breakthrough step followed by etching to form, below said mask, a stack of said polysilicon layer and said dielectric layer with exposed stack sidewalls on both thereof; form a blanket sidewall spacer layer of dielectric material filling said notch and covering said stack including said exposed stack sidewalls with said dielectric material; etch back said blanket sidewall spacer layer forming sidewall spacers composed of a dielectric material on said sidewalls and exposing said upper semiconductor surface aside from said sidewall spacers; and then form raised silicon source/drain regions on said upper semiconductor surface; whereby formation of spurious silicon nodules on said gate electrode proximate to said top surface of said gate electrode is inhibited. - View Dependent Claims (12, 13, 14, 15, 16)
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Specification