Method for making a semiconductor device comprising a lattice matching layer

• US 7,700,447 B2
• Filed: 02/21/2007
• Issued: 04/20/2010
• Est. Priority Date: 02/21/2006
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Yiptong, Jean Augustin Chan Sow Fook, Dukovski, Ilija, Halilov, Samed, Hytha, Marek, Mears, Robert J., Huang, Xiangyang, Stephenson, Robert John
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US11/677,099
• Publication Number:
  US 20070197006A1
• Time in Patent Office: 1,154 Days
• Field of Search: 438/285, 438/590, 438/602, 257/E21.124
• US Class Current: 438/285
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02439 Materials
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02499 Monolayers
• CPC Class Codes: H01L 21/02507 Alternating layers, e.g. superlattice
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/152 with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method for making a semiconductor device which may include forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer including a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice. More particularly, the superlattice may include a plurality of groups of layers, and each group of layers may include a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon. Furthermore, the at least one non-semiconductor monolayer may be constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween.

Claims

1. A method for making a semiconductor device comprising:

forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer comprising a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the first and second monocrystalline layers and comprising a superlattice;

the superlattice comprising a plurality of groups of layers, and at least one group of layers comprising a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon;

the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween.

2. The method of claim 1 further comprising converting at least a portion of the second monocrystalline layer to an oxide.

3. The method of claim 1 wherein the first and second lattice constants are different by not more than ten percent.

4. The method of claim 1 wherein the first material comprises a semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

5. The method of claim 1 wherein the second material comprises a semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

6. The method of claim 1 wherein the first material comprises silicon;

and wherein the second material comprises germanium.

7. The method of claim 1 wherein the second monocrystalline layer comprises a semiconductor;

and further comprising forming at least one active region in the second monocrystalline layer.

8. The method of claim 7 wherein forming the at least one active region comprises forming spaced apart source and drain regions defining a channel region therebetween.

9. The method of claim 8 further comprising forming a gate overlying the channel region.

10. The method of claim 1 wherein each base semiconductor portion comprises silicon.

11. The method of claim 1 wherein each base semiconductor portion comprises a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

12. The method of claim 1 wherein each non-semiconductor monolayer comprises oxygen.

13. The method of claim 1 wherein each non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.

14. A method for making a semiconductor device comprising:

forming a first monocrystalline layer comprising a first material having a first lattice constant, a second monocrystalline layer comprising a second material having a second lattice constant different than the first lattice constant, and a lattice matching layer between the first and second monocrystalline layers;

the lattice matching layer comprising at least one lower semiconductor monolayer adjacent the first monocrystalline layer, at least one upper semiconductor monolayer adjacent the second monocrystalline layer, and at least one non-semiconductor monolayer between the at least one lower and at least one upper semiconductor monolayers;

the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent upper and lower semiconductor monolayers, and at least some semiconductor atoms from the at least one upper and at least one lower semiconductor monolayers being chemically bound together through the at least one non-semiconductor monolayer therebetween.

15. The method of claim 14 further comprising converting at least a portion of the second monocrystalline layer to an oxide.

16. The method of claim 14 wherein the first and second lattice constants are different by not more than ten percent.

17. The method of claim 14 wherein the first and second materials comprise semiconductors selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors.

18. The method of claim 14 wherein the first material comprises silicon;

and wherein the second material comprises germanium.

19. The method of claim 14 wherein the second monocrystalline layer comprises a semiconductor, and further comprising forming spaced apart source and drain regions in the second monocrystalline layer defining a channel region therebetween.

20. The method of claim 19 further comprising forming a gate overlying the channel region.

21. The method of claim 14 wherein the at least one upper and at least one lower semiconductor monolayers comprise silicon.

22. The method of claim 14 wherein the at least one non-semiconductor monolayer comprises oxygen.

23. A method for making a semiconductor device comprising:

forming a first monocrystalline layer comprising silicon and having a first lattice constant;

forming a lattice matching layer on the first monocrystalline layer and comprising a superlattice;

the superlattice comprising a plurality of groups of layers, and each group of layers comprising a plurality of stacked semiconductor monolayers defining a semiconductor base portion and at least one non-semiconductor monolayer thereon;

the at least one non-semiconductor monolayer being constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together through the at least one non-semiconductor monolayer therebetween;

forming a second monocrystalline layer on the lattice matching layer comprising germanium and having a second lattice constant different than the first lattice constant; and

forming at least one active region in the second monocrystalline layer.

24. The method of claim 23 wherein the first and second lattice constants are different by not more than ten percent.

25. The method of claim 23 wherein forming the at least one active region comprises forming spaced apart source and drain regions in the second monocrystalline layer defining a channel region therebetween.

26. The method of claim 25 further comprising forming a gate overlying the channel region.

27. The method of claim 23 wherein each base semiconductor portion comprises silicon.

28. The method of claim 23 wherein each non-semiconductor monolayer comprises oxygen.