Semiconductor device and method for manufacturing the same

• US 7,700,998 B2
• Filed: 06/30/2008
• Issued: 04/20/2010
• Est. Priority Date: 07/03/2007
• Status: Expired due to Fees

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Okumura, Hideki, Nogami, Takayoshi, Misawa, Hiroto
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US12/164,389
• Publication Number:
  US 20090014788A1
• Time in Patent Office: 659 Days
• Field of Search: 257327-332, 257/E29.027, 257/E29.028, 257/E29.066, 257/E29.067, 438/259, 438/270
• US Class Current: 257/327
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.

Claims

1. A trench gate type semiconductor device with trench contact structure, comprising:

a first semiconductor layer of a first conductivity type formed above a main surface of a semiconductor substrate;

a second semiconductor layer of a second conductivity type formed on said first semiconductor layer;

a third semiconductor layer of said first conductivity type formed on said second semiconductor layer;

a plurality of gate electrodes which are formed in corresponding gate trenches via corresponding gate insulating films, said gate trenches being formed through said second semiconductor layer and said third semiconductor layer so as to run into said first semiconductor layer;

a plurality of impurity regions of said second conductivity type which are formed at regions below bottoms of corresponding contact trenches, said contact trenches being formed at said third semiconductor layer in a thickness direction thereof between corresponding ones of said gate trenches and longitudinal cross sections of said contact trenches being shaped in semiellipse, respectively;

first electrodes which are formed so as to embed said contact trenches and contacted with said impurity regions, respectively; and

a second electrode formed on a rear surface of said semiconductor substrate.

2. The semiconductor device as set forth in claim 1,

wherein said impurity regions are run into said second semiconductor layer from said third semiconductor layer.

3. The semiconductor device as set forth in claim 1,

further comprising a plurality of interlayer insulating films which are formed on said gate electrodes, respectively.

4. The semiconductor device as set forth in claim 3,

wherein top surfaces of said interlayer insulating films are positioned above bottoms of said contact trenches, respectively, so that sides of said contact trenches are closed by said interlayer insulating films and said interlayer insulating films function as etching stoppers.

5. The semiconductor device as set forth in claim 1,

wherein said first semiconductor layer functions as a drain layer, said second semiconductor layer functions as a base layer, said third semiconductor layer functions as a source layer, said first electrodes function as respective source electrodes and said second electrode functions as a drain electrode, so that said semiconductor device functions as a vertical field effect transistor.