Printed dopant layers

• US 7,701,011 B2
• Filed: 08/03/2007
• Issued: 04/20/2010
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Rockenberger, Joerg, Kamath, Arvind, Smith, Patrick, Zurcher, Fabio, Cleeves, James Montague
• Primary Examiner(s): Le; Thao X
• Assistant Examiner(s): Jones; Eric W
• Application Number:
  US11/888,942
• Publication Number:
  US 20080042212A1
• Time in Patent Office: 991 Days
• Field of Search: 257/369, 257/E21.119, 257/175, 257/413, 257/582, 257/E29.277, 257/148, 257/576, 438/199, 438/149, 438/151, 438/154
• US Class Current: 257/351
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

An electronic device, including a substrate, a plurality of first semiconductor islands on the substrate, a plurality of second semiconductor islands on the substrate, a first dielectric film on the first subset of the semiconductor islands, second dielectric film on the second semiconductor islands, and a metal layer in electrical contact with the first and second semiconductor islands. The first semiconductor islands and the first dielectric film contain a first diffusible dopant, and the second semiconductor islands and the second dielectric layer film contain a second diffusible dopant different from the first diffusible dopant. The present electronic device can be manufactured using printing technologies, thereby enabling high-throughput, low-cost manufacturing of electrical circuits on a wide variety of substrates.

Claims

1. An electronic device, comprising:

a) a substrate;

b) a plurality of first semiconductor islands on the substrate, the first semiconductor islands containing a first diffusible dopant;

c) a plurality of second semiconductor islands on the substrate, the second semiconductor islands containing a second diffusible dopant different from said first diffusible dopant;

d) a first dielectric film on said first subset of said semiconductor islands, said first dielectric film containing said first diffusible dopant and substantially free of said second diffusible dopant;

e) a second dielectric film on said second semiconductor islands and laterally adjacent to said first dielectric film, said second dielectric layer film containing said second diffusible dopant and substantially free of said first diffusible dopant; and

f) a metal layer in electrical contact with said first and second semiconductor islands.

2. The device of claim 1, wherein each of said semiconductor islands comprises a Group IVA element.

3. The device of claim 2, wherein said Group IVA element comprises silicon.

4. The device of claim 1, further comprising a gate dielectric layer on or over at least a subset of each of the first plurality and second plurality of semiconductor islands.

5. The device of claim 4, further comprising a gate on each of the gate dielectric layers.

6. The device of claim 5, further comprising contact holes in at least a subset of said first and second dielectric films, exposing at least part of an upper surface of the underlying gate and portions of each semiconductor island on opposed sides of each at least partially exposed gate.

7. The device of claim 6, wherein said metal layer is in contact with said upper surface of the exposed gate(s) and with the exposed portion(s) of said semiconductor islands.

8. The device of claim 5, wherein said gate comprises a metal silicide selected from the group consisting of nickel silicide, cobalt silicide, palladium silicide, platinum silicide, titanium silicide, tungsten silicide, and molybdenum silicide.

9. The device of claim 5, wherein said gate comprises a refractory metal selected from the group consisting of palladium, tungsten, and molybdenum.

10. The device of claim 5, wherein the gate dielectric layer is on an entire surface of the subset of each of the first plurality and second plurality of semiconductor islands, and the first and second dielectric layers are in physical contact with gate dielectric layer other than areas in contact with the gate.

11. The device of claim 4, wherein the first and second dielectric layers are in physical contact with said first and second pluralities of semiconductor islands.

12. The device of claim 1, wherein said gate comprises doped polysilicon, a metal silicide or a refractory metal.

13. The device of claim 1, wherein said metal layer comprises aluminum, silver, gold, copper, palladium or platinum.

14. The device of claim 1, wherein the first dopant comprises an N-type dopant and the second dopant comprises a P-type dopant.

15. The device of claim 14, wherein the first dopant comprises phosphorous and the second dopant comprises boron.

16. The device of claim 1, wherein the first and second dielectric films overlap.

17. The device of claim 1, wherein the first and second pluralities of semiconductor islands are in an array, said first semiconductor islands dielectric layer are in a first group of said array, and said second semiconductor islands are in a second group of said array.

18. The device of claim 1, wherein the first and second dielectric layers are in physical contact with said first and second pluralities of semiconductor islands.

19. The device of claim 1, wherein each of said first and second pluralities of semiconductor islands contain source/drain terminals.