Power core devices

• US 7,701,052 B2
• Filed: 08/31/2006
• Issued: 04/20/2010
• Est. Priority Date: 10/21/2005
• Status: Active Grant

• Current Assignee: Chemtron Research LLC (Intellectual Ventures LLC)
• Original Assignee: E. I. du Pont de Nemours and Company (Corteva, Inc.)
• Inventors: Ferguson, Saul, Borland, William J.
• Primary Examiner(s): Andújar; Leonardo
• Assistant Examiner(s): HARRISTON, WILLIAM A
• Application Number:
  US11/514,094
• Publication Number:
  US 20070090511A1
• Time in Patent Office: 1,328 Days
• Field of Search: 257/499, 257/500, 257/501, 257/516, 257/532, 257/528, 257/691, 257/700, 361/321, 29/250.3, 174/262
• US Class Current: 257/700
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/0102 Calcium [Ca]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/113 Via provided in pad; Pad over filled via
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/09763 Printed component having superposed conductors, but integrated in one circuit layer
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array

Abstract

A device comprising a power core wherein said power core comprises: at least one embedded singulated capacitor layer containing at least one embedded singulated capacitor wherein said embedded singulated capacitor comprises at least a first electrode and a second electrode and wherein said embedded singulated capacitor is positioned on the outer layer of the power core with both first and second electrodes of the capacitor on the outer layer of the power core so that at least one Vcc (power) terminal and at least one Vss (ground) terminal of a semiconductor device can be directly connected to at least one first and at least one second electrode, respectively.

Claims

1. A device comprising a semiconductor and a power core having an exterior surface on which the semiconductor is mounted wherein the power core comprises:

at least one embedded singulated capacitor layer containing multiple embedded singulated individual capacitors wherein said embedded singulated individual capacitors each comprise at least a first electrode and a second electrode and wherein said embedded singulated individual capacitors are positioned proximate the exterior surface of the power core with the first and second electrodes of said embedded singulated individual capacitors each including electrode pads that are exposed on the exterior surface of the power core;

at least one planar capacitor laminate embedded within the power core, wherein the at least one planar capacitor laminate has a first electrode and a second electrode, and wherein the first electrodes of said multiple embedded singulated individual capacitors are electrically connected to the first electrode of the at least one planar capacitor laminate and the second electrodes of said multiple embedded singulated individual capacitors are electrically connected to the second electrode of the at least one planar capacitor laminate, such that said embedded singulated individual capacitors are connected in parallel to said at least one planar capacitor laminate and said planar capacitor laminate serves as a low inductance path to supply a charge to said embedded singulated individual capacitors; and

wherein the semiconductor has Vcc (power) terminals and Vss (ground) terminals, and Vcc (power) terminals of the semiconductor are connected to first electrodes of the multiple embedded singulated individual capacitors and Vss (ground) terminals of the semiconductor are connected to second electrodes of the multiple embedded singulated individual capacitors.

2. The device of claim 1 wherein said power core contains at least one signal layer.

3. The device of claim 1 wherein additional passive components are connected to and external to said power core.

4. The device of claim 1 wherein the first and second electrodes of said more than one embedded singulated individual capacitors are in the same plane.

5. The device of claim 1 wherein said embedded singulated individual capacitors comprise formed on foil ceramic capacitors.

6. The device of claim 5 wherein each of said embedded singulated individual formed on foil ceramic capacitors comprises a fired on foil ceramic capacitor.

7. The device of claim 1 wherein said semiconductor is a microprocessor.