Stacked die network-on-chip for FPGA

• US 7,701,252 B1
• Filed: 03/03/2008
• Issued: 04/20/2010
• Est. Priority Date: 11/06/2007
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Chow, Francis Man-Chit, Patel, Rakesh H., Pistorius, Erhard Joachim
• Primary Examiner(s): Tran; Anh Q
• Application Number:
  US12/074,467
• Time in Patent Office: 778 Days
• Field of Search: 326/39, 326/41, 326/47, 326/101
• US Class Current: 326/41
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.

Claims

1. An apparatus, comprising:

a network-on-chip (NoC) die layer;

a programmable chip die layer including a plurality of programmable chip blocks;

a plurality of connectors coupling the NoC die layer and the programmable die layer, wherein the NoC die layer includes interconnection circuitry operable to connect the plurality of programmable chip blocks; and

one or more multiplexers wherein one of multiple inputs or an output is orthogonal to a plane of the other inputs and output.

2. The apparatus of claim 1, wherein the programmable chip blocks are building blocks including logic elements and digital signal processing (DSP) blocks.

3. The apparatus of claim 1, wherein the programmable chip blocks are building blocks selected from a group consisting of phase lock loops (PLLs), input/output (I/O) cells, memory blocks, digital signal processing (DSP) blocks and logic elements.

4. The apparatus of claim 1, wherein the NoC die layer is an Application Specific Integrated Circuit (ASIC).

5. The apparatus of claim 1, wherein the programmable chip die layer is a field programmable gate array (FPGA).

6. The apparatus of claim 1, wherein the NoC layer comprises an FPGA die layer.

7. The apparatus of claim 1, wherein the plurality of vertical connectors are selected from a group consisting of vertical interconnects, micro bumps, bond pads, and a combination thereof.

8. The apparatus of claim 1, wherein the NoC die layer comprises a plurality of non-blocking interconnect switches, interconnects, and a communication interface to the connectors selected from a group consisting of a time multiplexer, a source synchronous interface, and a high speed serial interface.

9. The apparatus of claim 8, wherein the high speed serial interface is a low voltage differential signaling (LVDS) transceiver or a serializer/deseralizer (SerDes) transceiver.

10. The apparatus of claim 8, wherein the NoC die layer further comprises memory blocks.

11. The apparatus of claim 8, wherein the NoC die layer further comprises direct memory access (DMA) engines.

12. The apparatus of claim 10, wherein one or more memory blocks are connected to external components via dedicated connections.

13. The apparatus of claim 1, wherein the programmable die layer is partitioned into 2^N segments that are each coupled to the NoC die layer.

14. The apparatus of claim 1, further comprising an additional programmable chip die layer including a plurality of programmable chip building blocks, wherein the additional programmable chip die layer is connected to the NoC die layer.

15. A device, comprising:

a first number of die layers selected individually from a group of die layers consisting of a FPGA die, a Programmable Logic Device (PLD) die, a Complex Programmable Logic Devices (CPLD) die, a microprocessor die, a memory die and other die having one or more IP cores;

a second number of network-on-chip (NoC) die layers interposed between the first number of die layers; and

a plurality of connectors coupling each NoC die layer to one or more adjacent die layers, wherein each NoC die layer comprises a plurality of non-blocking interconnect switches, interconnects, and a communication interface to the connectors selected from a group consisting of a time multiplexer, a source synchronous interface, and a high speed serial interface;

wherein the first number equals the second number plus one.

16. An apparatus, comprising:

a network-on-chip (NoC) layer,

a programmable layer including a plurality of programmable elements; and

means for coupling the NoC layer and the programmable layer to operably connect two or more of the plurality of programmable elements

one or more multiplexers wherein one of multiple inputs or an output is orthogonal to a plane of the other inputs and output.

17. An apparatus, comprising:

a network-on-chip (NoC) die layer;

a programmable chip die layer including a plurality of programmable chip blocks; and

a plurality of connectors coupling the NoC die layer and the programmable die layer, wherein the NoC die layer includes interconnection circuitry operable to connect the plurality of programmable chip blocks, further wherein the NoC die layer comprises a plurality of non-blocking interconnect switches, interconnects, and a communication interface to the connectors selected from a group consisting of a time multiplexer, a source synchronous interface, and a high speed serial interface.

18. The apparatus of claim 17, wherein the high speed serial interface is a low voltage differential signaling (LVDS) transceiver or a serializer/deseralizer (SerDes) transceiver.

19. The apparatus of claim 17, wherein the NoC die layer further comprises memory blocks.

20. The apparatus of claim 17, wherein the NoC die layer further comprises direct memory access (DMA) engines.