Display panel having a substratum and a plurality of scan lines formed on the substratum, a display device, and electronic device thereof
First Claim
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1. A panel comprising:
- a substratum;
a plurality of scan lines formed on the substratum;
a plurality of data lines intersecting with the plurality of scan lines wherein the plurality of data lines are formed on the substratum;
a plurality of pixels disposed at locations where the plurality of scan lines intersect with the plurality of data lines; and
a peripheral circuit formed on the substratum;
wherein the peripheral circuit includes first and second processes, and the first and second processes are controlled by means of event driving, and the first process requires the second process to forward data, and the second process forwards the data to the first process,wherein the first process includes a first port, and the second process includes a second port, and the first and second ports are connected via a channel, and a req signal and an ack signal are sent or received between the first and second ports,wherein the second port senses the req signal when the first port raises a level of the req signal from an L level to an H level, and the second port raises a level of the ack signal from the L level to the H level when sensing the req signal, and the first port senses a transition of the ack signal when the level of the ack signal is raised from the L level to the H level, and the first port lowers the level of the req signal from the H level to the L level,wherein the peripheral circuit further includes a rendezvous circuit, the first port includes an encoder, and the second port includes a decoder, and data is sent from the first port to the second port, and the data received by the second port is input to the rendezvous circuit,wherein the rendezvous circuit performs a function so that a next transaction of sending and receiving request and acknowledge signals is not started until all the transactions that are in progress have ended.
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Abstract
It is an object of the present invention to propose a sheet computer that eliminates the drawback in operational speed caused by clock delays of a system clock and that is capable of high speed operation. In order to achieve this object, in the sheet computer of the present invention, a display circuit and peripheral circuits connected to the display circuit are fabricated on the same substratum and the peripheral circuits constitute an asynchronous system without global clocking. In the asynchronous system, processes constituting minimum function circuits perform mutual handshaking by channels and drive events actively or passively. The asynchronous system does not use global clocking and it is therefore possible to implement lower power consumption and a higher operational speed.
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Citations
13 Claims
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1. A panel comprising:
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a substratum; a plurality of scan lines formed on the substratum; a plurality of data lines intersecting with the plurality of scan lines wherein the plurality of data lines are formed on the substratum; a plurality of pixels disposed at locations where the plurality of scan lines intersect with the plurality of data lines; and a peripheral circuit formed on the substratum; wherein the peripheral circuit includes first and second processes, and the first and second processes are controlled by means of event driving, and the first process requires the second process to forward data, and the second process forwards the data to the first process, wherein the first process includes a first port, and the second process includes a second port, and the first and second ports are connected via a channel, and a req signal and an ack signal are sent or received between the first and second ports, wherein the second port senses the req signal when the first port raises a level of the req signal from an L level to an H level, and the second port raises a level of the ack signal from the L level to the H level when sensing the req signal, and the first port senses a transition of the ack signal when the level of the ack signal is raised from the L level to the H level, and the first port lowers the level of the req signal from the H level to the L level, wherein the peripheral circuit further includes a rendezvous circuit, the first port includes an encoder, and the second port includes a decoder, and data is sent from the first port to the second port, and the data received by the second port is input to the rendezvous circuit, wherein the rendezvous circuit performs a function so that a next transaction of sending and receiving request and acknowledge signals is not started until all the transactions that are in progress have ended. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification
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Current AssigneeSeiko Epson Corporation (Seiko Group)
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Original AssigneeSeiko Epson Corporation (Seiko Group)
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InventorsKaraki, Nobuo
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Primary Examiner(s)Nguyen, Chanh
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Assistant Examiner(s)Karimi, Pegeman
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Application NumberUS10/797,054Publication NumberTime in Patent Office2,231 DaysField of Search345/7, 345/8, 345/85, 345/87, 345/204, 345/205, 345/206, 362/103, 712/E9.063, 326/63, 716/3, 716/5US Class Current345/87CPC Class CodesG06F 1/10 Distribution of clock signa...G06F 1/16 Constructional details or a...G06F 1/1613 for portable computers cool...G06F 1/163 Wearable computers, e.g. on...G06F 1/1637 Details related to the disp...G06F 1/1639 the display being based on ...G09G 2300/0408 Integration of the drivers ...G09G 2330/021 Power management, e.g. powe...G09G 3/3611 Control of matrices with ro...G09G 3/3648 using an active matrix G09G...H01L 23/4985 Flexible insulating substra...H01L 2924/00 Indexing scheme for arrange...H01L 2924/0002 Not covered by any one of g...
